View MB90P214A_5114188.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

ds07-13501-6e fujitsu semiconductor data sheet 16-bit proprietary microcontroller cmos f 2 mc-16f mb90210 series mb90214/p214a/p214b/w214a/w214b/v210 n outline the mb90210 series is a line of 16-bit microcontrollers particularly suitable for system control of video cameras, vtrs, and copiers. the f 2 mc-16f cpu integrated in this series is based on the f 2 mc*-16, while providing enhanced instructions for high-level languages and supporting extended addressing modes. the mb90210 series incorporates a variety of peripheral resources such as a pwc timer with 4 channels, a 10- bit a/d converter with 8 channels, uart serial ports with 3 channels (1 channel for cts and 1 channel for dual input/output pin switching), 16-bit reload timers with 8 channels, and an 8-bit ppg timer with 1 channel. mb90p214b/w214b is under development. *: f 2 mc stands for fujitsu flexible microcontroller. n pac k ag e 80-pin plastic qfp (fpt-80p-m06) 80-pin ceramic qfp (fpt-80c-c02)
mb90210 series 2 n features f 2 mc-16f cpu ? minimum execution time: 62.5 ns/16-mhz oscillation (using a duty control system) ? instruction sets optimized for controllers upward object-compatible with the f 2 mc-16(h) various data types (bit, byte, word, and long-word) instruction cycle improved to speed up operation extended addressing modes: 25 types high coding efficiency access method (bank access with linear pointer) enhanced multiplication and division instructions (with signed instructions added) higher-precision operation using a 32-bit accumulator ? extended intelligent i/o service (automatic transfer function independent of instructions) access area expanded to 64 kbytes ? enhanced instruction set applicable to high-level language (c) and multitasking system stack pointer enhanced pointer-indirect instructions barrel shift instruction stack check function ? increased execution speed: 8-byte instruction queue ? powerful interrupt functions: 8 levels and 29 sources integrated peripheral resources ? rom : 64 kbytes (mb90214) eprom : 64 kbytes (mb90w214a/w214b) otprom: 64kbytes (MB90P214A/p214b) ? ram: 3 kbytes (mb90214) 4 kbytes (MB90P214A/p214b/w214a/w214b/v210) ? general-purpose ports: max. 65 channels ? pwc timer with time measurement function: 4 channels ? 10-bit a/d converter: 8 channels ? uart: 3 channels ? including: 1 channel with cts function 1 channel with i/o pin switching function ? 16-bit reload timer toggled output, external clock, and gate functions: 4 channels external clock and gate functions: 4 channels ? 8-bit ppg timer: 1 channel ? dtp/external-interrupt inputs: 4 channels ? write-inhibit ram: 256 bytes (mb90v210: 512 bytes) ? timebase counter: 18 bits ? clock gear function ? low-power consumption mode sleep mode stop mode hardware standby mode
3 mb90210 series product description ? mb90214 is a mask rom product. ? MB90P214A/p214b are otprom products. ? mb90w214a/w214b are eprom products. es only. ? operating temperature of MB90P214A/w214a is C40 c to +85 c. (however, the ac characteristics is assured in C40 c to +70 c) ? mb90v210 is a evaluation device for the program development. es only.
mb90210 series 4 n product lineup MB90P214A mb90p214b mb90w214a mb90w214b mb90v210 classification mask rom product otprom product eprom product for evaluation rom size 64 kbytes 64 kbytes 64 kbytes ram size 3 kbytes 4 kbytes 4 kbytes 4 kbytes cpu functions the number of instructions: 412 instruction bit length: 8 or 16 bits instruction length: 1 to 7 bytes data bit length: 1, 4, 8, 16, or 32 bits minimum execution time: 62.5 ns/16 mhz interrupt processing time: 1.0 m s/16 mhz (min.) ports i/o ports (n-ch open-drain): 8 i/o ports (cmos): 57 total: 65 pwc timer number of channels: 4 16-bit reload timer operation (operating clock cycle: 0.25 m s to 1.31 ms) 16-bit pulse-width count operation (allowing continuous/one-shot measurement, h/l width measurement, inter-edge measurement, and divided-frequency measurement) 10-bit a/d converter resolution: 10 or 8 bits, number of inputs: 8 single conversion mode (conversion for each input channel) scan conversion mode (continuous conversion for up to 8 consecutive channels) continuous conversion mode (repeated conversion for a selected channel) stop conversion mode (conversion every fixed cycle) uart number of channels: 3 (1 channel with cts function; 1 channel with i/o pin switching function) clock-synchronous transfer mode (full-duplex double buffering, 7- to 9-bit data length, 2400 to 62500 bps) asynchronous transfer mode (full-duplex double buffering, 7- to 9-bit data length, 2400 to 62500 bps) timer number of channels: 4 channels 2 types 16-bit reload timer operation (operating clock cycle: 0.25 m s to 1.05 s) 8-bit ppg timer number of channels: 1 8-bit ppg operation (operating clock cycle: 0.25 m s to 6 s) dtp/external interrupt number of inputs: 4 external interrupt mode (allowing interrupts to activate at four different request levels) simple dma start mode (allowing extended i 2 os to activate at two different request levels) write-inhibit ram ram size: 256 bytes (mb90v210: 512 bytes) ram write-protectable with wi pin standby mode stop mode (activated by software or hardware) and sleep mode gear function machine clock operating frequency switching: 16, 8, 4, or 1 mhz (at 16 mhz oscillation) package fpt-80p-m06 fpt-80c-c02 pga-256c-a02 mb90214 part number item
5 mb90210 series n differences between mb90214 (mask rom product) and MB90P214A/p214b/ w214a/w214b note: mb90v210, device used for evaluation, is not warranted for electrical specifications. MB90P214A mb90p214b mb90w214a mb90w214b rom mask rom 64 kbytes otprom 64 kbytes eprom 64 kbytes pin function 43 pins md2 pin md2/v pp pin mb90214 part number item
mb90210 series 6 n pin assignment x1 v cc p00/d00 p01/d01 p02/d02 p03/d03 p04/d04 p05/d05 p06/d06 p07/d07 p10/d08 p12/d10 p13/d11 p14/d12 p15/d13 p11/d09 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 x0 v ss rst p57/wi p56/rd p55/wrl p54/wrh/cts0/int3 p53/hrq p52/hak p51/rdy p50/clk p82/int2/atg p81/int1 p80/int0 p75/sod0 p74/sid0 p73/sck0 p72/sod1 p71/sid1 p70/sck1 hst md2 md1 md0 p16d14 p17d15 p20a00/tin0 p21/a01/tin1 p22/a02/tin2 p23/a03/tin3 p24/a04/tin4 p25/a05/tin5 p26/a06/tin6 p27/a07/tin7 v ss p 31/a09/ ppg p32/a10/tout0 p36/a14/sck3 p37/a15/s i d3 p40/a16/sod3 p30/a08 p34/a12/tout2 p41/a17/sc k2 p42/a18/s i d2 p43/a19/s od2 p44/a20/ pwc0/pout0 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 p67/an7 p66/an6 p65/an5 p64/an4 p63/an3 p62/an2 v ss p61/an1 p60/an0 av ss avrl av cc pwc3/p47/a23/pout3 pwc2/p46/a22/pout2 pwc1/p45/a21/pout1 avrh (top view) (fpt-80p-m06) (fpt-80c-c02) 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 p33/a11/tout1 p35/a13/tout3
7 mb90210 series n pin description * : fpt-80p-m06, fpt-80c-c02 (continued) pin no. pin name circuit type function qfp* 64, 65 x0, x1 a crystal oscillator pins (16 mhz) 62 rst h external reset request input pin 66 v cc power supply digital circuit power supply pin 11, 34, 63 v ss power supply digital circuit grounding level 67 to 74 p00 to p07 b general-purpose i/o ports these ports are available only in the single-chip mode. d00 to d07 i/o pins for the lower eight bits of external data bus these pins are available in an external-bus mode. 75 to 80, 1, 2 p10 to p15, p16, p17 b general-purpose i/o ports these ports are available in the single-chip mode and in an external-bus mode with the 8-bit data bus specified. d08 to d13, d14, d15 i/o pins for the upper eight bits of external data bus these pins are available in an external-bus mode with the 16-bit data bus specified. 3 to 6 p20 to p23 e general-purpose i/o ports these ports are available only in the single-chip mode. a00 to a03 output pins for external address buses a00 to a03 these pins are available in an external-bus mode. tin0 to tin3 16-bit reload timer 1 (ch.0 to ch.3) input pins these pins are available when the 16-bit reload timer 1 (ch.0 to ch.3) input specification is enabled. the data on the pin is read as the 16-bit reload timer 1 (ch.0 to ch.3) input (tin0 to tin3). 7 to 10 p24 to p27 e general-purpose i/o ports these ports are available only in the single-chip mode. a04 to a07 output pins for external address buses a04 to a07 these pins are available in an external-bus mode. tin4 to tin7 16-bit reload timer 2 (ch.4 to ch.7) input pins these pins are available when the 16-bit reload timer 2 (ch.4 to ch.7) input specification is enabled. the data on the pin is read as the 16-bit reload timer 2 (ch.4 to ch.7) input (tin4 to tin7). 12 p30 e general-purpose i/o port this port is available in the single-chip mode or when the middle address control register setting is port. a08 output pin for external address bus a08 this pin is available in an external-bus mode and when the middle address control register set to address.
mb90210 series 8 * : fpt-80p-m06, fpt-80c-c02 (continued) pin no. pin name circuit type function qfp* 13 p31 e general-purpose i/o port this port is available in the single-chip mode or when the middle address control register setting is port, with the 8-bit ppg output is disabled. a09 output pin for external address bus a09 this pin is available in an external-bus mode and when the middle address control register setting is address. ppg ppg timer output pin this pin is available when the ppg operation mode control register specification is the ppg output pin. 14 to 17 p32 to p35 e general-purpose i/o ports these ports are available in the single-chip mode or when the middle address control register setting is port, with the 16-bit reload timer 1 (ch.0 to ch.3) output is disabled. a10 to a13 output pins for external address buses a10 to a13 these pins are available in an external-bus mode and when the middle address control register setting is address. tout0 to tout3 16-bit reload timer 1 (ch.0 to ch.3) output pin these pins are available when the 16-bit reload timer 1 (ch.0 to ch.3) is output operation. 18 p36 e general-purpose i/o port this port is available when the uart (ch.2) clock output is disabled either in the single-chip mode or when the middle address control register setting is port. a14 output pin for external address bus a14 this pin is available when the uart (ch.2) clock output is disabled in an external-bus mode and when the middle address control register setting is address. sck3 uart (ch.2) clock output pin (sck3) this pin is available when the uart (ch.2) clock output is enabled. uart (ch.2) external clock input pin (sck3) this pin is available when the port is in input mode and the uart (ch.2) specification is external clock mode. 19 p37 e general-purpose i/o port this port is available in the single-chip mode or when the middle address control register setting is port. a15 output pin for external address bus a15 this pin is available in an external-bus mode and when middle address control register setting is address. sid3 uart (ch.2) serial data input pin (sid3) since this input is used whenever the sid3 is in input operation, the output by any other function must be suspended unless the output is intentionally performed.
9 mb90210 series * : fpt-80p-m06, fpt-80c-c02 (continued) pin no. pin name circuit type function qfp* 20 p40 e general-purpose i/o port this port is available when the uart (ch.2) serial data output from sod3 is disabled either in the single-chip mode or when the upper address control register setting is port. a16 output pin for external address bus a16 this pin is available when the uart (ch.2) serial data output from sod3 is disabled in an external-bus mode and when the upper address control register setting is address. sod3 uart (ch.2) serial data output pin (sod3) this pin is available when the uart (ch.2) serial data output is enabled. 21 p41 e general-purpose i/o port this port is available when the uart (ch.2) clock output is disabled either in the single-chip mode or when the upper address control register setting is port. a17 output pin for external address bus a17 this pin is available when the uart (ch.2) clock output is disabled in an external-bus mode and when the upper address control register setting is address. sck2 uart (ch.2) clock output pin (sck2) this pin is available when the uart (ch.2) clock output is enabled. uart (ch.2) external clock input pin (sck2) this pin is available when the port is in input mode and the uart (ch.2) specification is external clock mode. 22 p42 e general-purpose i/o port this port is available in the single-chip mode or when the upper address control register setting is port. a18 output pin for external address bus a18 this pin is available in an external-bus mode and when the upper address control register setting is address. sid2 uart (ch.2) serial data input pin (sid2) since this input is used whenever the sid2 is in input operation, the output by any other function must be suspended unless the output is intentionally performed. 23 p43 e general-purpose i/o port this port is available when the uart (ch.2) serial data output from sod2 is disabled either in the single-chip mode or when the upper address control register setting is port. a19 output pin for external address bus a19 this pin is available when the uart (ch.2) serial data output from sod2 is disabled in an external-bus mode and when the upper address control register setting is address. sod2 uart (ch.2) serial data output pin (sod2) this pin is available when the uart (ch.2) serial data output from sod2 is enabled.
mb90210 series 10 * : fpt-80p-m06, fpt-80c-c02 (continued) pin no. pin name circuit type function qfp* 24 pwc0 e pwc timer input pin since this input is used whenever the pwc0 timer is in input operation, the output by any other function must be suspended unless the output is intentionally performed. pout0 pwc timer output pin this pin is available when the pwc0 is output operation. 25 p45 e general-purpose i/o port this port is available in the single-chip mode or when the upper address control register setting is port. a21 output pin for external address bus a21 this pin is available in an external-bus mode and when the upper address control register setting is address. pwc1 pwc timer data sample input pin since this input is used whenever the pwc1 timer is in input operation, the output by any other function must be suspended unless the output is intentionally performed. pout1 pwc timer output pin this pin is available when the pwc1 is output operation. 26 p46 e general-purpose i/o port this port is available in the single-chip mode or when the upper address control register setting is port. a22 output pin for external address bus a22 this pin is available in an external-bus mode and when the upper address control register setting is address. pwc2 pwc timer input pin since this input is used whenever the pwc2 timer is in input operation, the output by any other function must be suspended unless the output is intentionally performed. pout2 pwc timer output pin this pin is available when the pwc2 is output operation. 27 p47 e general-purpose i/o port this port is available in the single-chip mode or when the upper address control register setting is port. a23 output pin for external address bus a23 this pin is available in an external-bus mode and when the upper address control register setting is address. pwc3 pwc timer input pin since this input is used whenever the pwc3 timer is in input operation, the output by any other function must be suspended unless the output is intentionally performed. pout3 pwc timer output pin this pin is available when the pwc3 is output operation.
11 mb90210 series * : fpt-80p-m06, fpt-80c-c02 (continued) pin no. pin name circuit type function qfp* 54 p50 e general-purpose i/o port this port is available in the single-chip mode and when the clk output is disabled. clk clk output pin this pin is available in an external-bus mode with the clk output enabled. 55 p51 e general-purpose i/o port this port is available in the single-chip mode or when the ready function is disable. rdy ready signal input pin this pin is available in an external-bus mode and when the ready function is enabled. 56 p52 e general-purpose i/o port this port is available in the single-chip mode or when the hold function is disabled. hak hold acknowledge output pin this pin is available in an external-bus mode and when the hold function is enabled. 57 p53 e general-purpose i/o port this port is available in the single-chip mode or when the hold function is disabled in an external-bus mode. hrq hold request input pin this pin is available in an external-bus mode and when the hold function is enabled. since this input is used during this operation at any time, the output by any other function must be suspended unless the output is intentionally performed. 58 p54 d general-purpose i/o port this port is available in the single-chip mode, in the external bus 8-bit mode, or when the wrh pin output is disabled. when these pins are open in input mode, through current may leak in stop mode/reset mode, be sure to fix these pins to v cc /v ss level to use these pins in input mode. cts0 uart (ch.0) clear-to-send input pin since this input is used whenever the uart (ch.0) cts function is enabled, the output by any other function must be suspended unless the output is intentionally performed. when these pins are open in input mode, through current may leak in stop mode/reset mode, be sure to fix these pins to v cc /v ss level to use these pins in input mode. wrh write strobe output pin for the upper eight bits of data bus this pin is available in the external bus 16-bit mode with the wrh pin output enabled in an external-bus mode.
mb90210 series 12 * : fpt-80p-m06, fpt-80c-c02 (continued) pin no. pin name circuit type function qfp* 58 int3 d external interrupt request input pin since this input is used whenever external interrupts are enabled, the output by any other function must be suspended unless the output is intentionally performed. when these pins are open in input mode, through current may leak in stop mode/reset mode, be sure to fix these pins to v cc /v ss level to use these pins in input mode. 59 p55 e general-purpose i/o port this port is available in the single-chip mode or when the wrl pin output is disabled. wrl write strobe output pin for the lower eight bits of data bus this pin is available in an external-bus mode and when the wrl pin output is enabled. 60 p56 e general-purpose i/o port this port is available in the single-chip mode. rd data bus read strobe output pin this pin is available in an external-bus mode. 61 p57 d general-purpose i/o port this port is always available. when these pins are open in input mode, through current may leak in stop mode/reset mode, be sure to fix these pins to v cc /v ss level to use these pins in input mode. wi ram write disable request input since this input is used during this operation at any time, the output by any other function must be suspended unless the output is intentionally performed. when these pins are open in input mode, through current may leak in stop mode/reset mode, be sure to fix these pins to v cc /v ss level to use these pins in input mode. 32, 33, 35 to 40 p60, p61, p62 to p67 c open-drain i/o ports these ports are available when the analog input enable register setting is port. an0, an1, an2 to an7 10-bit a/d converter analog input pins these pins are available when the analog input enable register setting is analog input. 41 to 43 md0 to md2 f operation mode select signal input pins connect these pins directly to v cc or v ss . 44 hst g hardware standby input pin 45 p70 e general-purpose i/o port this port is available when the uart (ch.1) clock output is disabled.
13 mb90210 series * : fpt-80p-m06, fpt-80c-c02 (continued) pin no. pin name circuit type function qfp* 45 sck1 e uart (ch.1) clock output pin this pin is available when the uart (ch.1) clock output is enabled. uart (ch.1) external clock input pin this pin is available when the port is in input mode and the uart (ch.1) specification is external clock mode. 46 p71 e general-purpose i/o port this port is always available. sid1 uart (ch.1) serial data input pin since this input is used whenever the uart (ch.1) is in input operation, the output by any other function must be suspended unless the output is intentionally performed. 47 p72 e general-purpose i/o port this port is available when the uart (ch.1) serial data output is disabled. sod1 uart (ch.1) serial data output pin this pin is available when the uart (ch.1) serial data output is enabled. 48 p73 e general-purpose i/o port this port is available when the uart (ch.0) clock output is disabled. sck0 uart (ch.0) clock output pin this pin is available when the uart (ch.0) clock output is enabled. uart (ch.0) external clock input pin this pin is available when the port is in input mode and the uart (ch.0) specification is external clock mode. 49 p74 e general-purpose i/o port this port is always available. sid0 uart (ch.0) serial data input pin since this input is used whenever the uart (ch.0) is in input operation, the output by any other function must be suspended unless the output is intentionally performed. 50 p75 e general-purpose i/o port this port is available when the uart (ch.0) serial data output is disabled. sod0 uart (ch.0) serial data output pin this pin is available when the uart (ch.0) serial data output is enabled. 51, 52 p80, p81 d general-purpose i/o port this port is always available. when these pins are open in input mode, through current may leak in stop mode/reset mode, be sure to fix these pins to v cc /v ss level to use these pins in input mode.
mb90210 series 14 (continued) * : fpt-80p-m06, fpt-80c-c02 pin no. pin name circuit type function qfp* 51, 52 int0, int1 d external interrupt request input pin since this input is used whenever external interrupts are enabled, the output by any other function must be suspended unless the output is intentionally performed. when these pins are open in input mode, through current may leak in stop mode/reset mode, be sure to fix these pins to v cc /v ss level to use these pins in input mode. 53 p82 d general-purpose i/o port this port is always available. when these pins are open in input mode, through current may leak in stop mode/reset mode, be sure to fix these pins to v cc /v ss level to use these pins in input mode. int2 external interrupt request input pin since this input is used whenever external interrupts are enabled, the output by any other function must be suspended unless the output is intentionally performed. when these pins are open in input mode, through current may leak in stop mode/reset mode, be sure to fix these pins to v cc /v ss level to use these pins in input mode. at g 10-bit a/d converter trigger input pin when these pins are open in input mode, through current may leak in stop mode/reset mode, be sure to fix these pins to v cc /v ss level to use these pins in input mode. 28 av cc power supply analog circuit power supply pin this power supply must be turned on or off with a potential equal to or higher than av cc applied to v cc . be sure that av cc = v cc before use and during operation. 29 avrh power supply analog circuit reference voltage input pin this pins must be turned on or off with a potential equal to or higher than avrh applied to av cc . 30 avrl power supply analog circuit reference voltage input pin 31 av ss power supply analog circuit grounding level
15 mb90210 series n i/o circuit type (continued) type circuit remarks a ? oscillation feedback resistor: approx.1 m w mb90214 mb90p214b mb90w214b ? oscillation feedback resistor: approx.1 m w MB90P214A mb90w214a b ? cmos-level i/o standby control provided mb90214: with or without pull-up/pull-down reisistor optional MB90P214A/p214b: without pull-up/pull-down resistor mb90w214a/w214b: without pull-up/pull-down resistor c ? n-ch open-drain output ? cmos-level hysteresis input a/d control provided d ? cmos-level output ? cmos-level hysteresis input standby control not provided mb90214: with or without pull-up/pull-down reisistor optional MB90P214A/p214b: without pull-up/pull-down resistor mb90w214a/w214b: without pull-up/pull-down resistor x1 x0 standby control x1 x0 standby control digital output digital output digital input standby control r r r digital input digital output a/d input r digital output digital output digital input r r r
mb90210 series 16 (continued) note: the pull-up and pull-down resistors are always connected, regardless of the state. type circuit remarks e ? cmos-level output ? cmos-level hysteresis input standby control provided mb90214: with or without pull-up/pull-down reisistor optional MB90P214A/p214b: without pull-up/pull-down resistor mb90w214a/w214b: without pull-up/pull-down resistor f ? cmos-level input with no standby control mask rom products only: md2: with pull-down resistor md1: with pull-up resistor md0: with pull-down resistor ? coms-level input with no standby control md2 of otprom products/eprom products only g ? cmos-level hysteresis input standby control not provided ? with input analog filter (40 ns typ.) h ? cmos-level hysteresis input standby control not provided ? with input analog filter (40 ns typ.) ? with pull-up resistor mb90214: with or without pull-up/pull-down resistor optional MB90P214A/w214a/p214b/w214b: with pull-up resistor digital input digital output digital output r r r digital input r digital input r v pp power supply r analog filter digital input pull-up resistor r r digital input analog filter : p-type transistor : n-type transistor
17 mb90210 series n handling devices 1. preventing latchup cmos ics may cause latchup when a voltage higher than v cc or lower than v ss is applied to input or output pins, or when a voltage exceeding the rating is applied between v cc and v ss . if latch-up occurs, the power supply current increases rapidly, sometimes resulting in thermal breakdown of the device. use meticulous care not to let any voltage exceed the maximum rating. also, take care to prevent the analog power supply (av cc and avrh) and analog input from exceeding the digital power supply (v cc ) when the analog system power supply is turned on and off. 2. treatment of unused input pins leaving unused input pins open could cause malfunctions. they should be connected to a pull-up or pull-down resistor. 3. treatment of pins when a/d is not used connect to be av cc = avrh = v cc and av ss = avrl = v ss even if the a/d converter is not in use. 4. precautions when using an external clock to reset the internal circuit properly by the low-level input to the rst pin, the l level input to the rst pin must be maintained for at least five machine cycles. pay attention to it if the chip uses external clock input. 5. v cc and v ss pins apply equal potential to the v cc and v ss pins. 6. supply voltage variation the operation assurance range for the v cc supply voltage is as given in the ratings. however, sudden changes in the supply voltage can cause misoperation, even if the voltage remains within the rated range. therefore, it is important to supply a stable voltage to the ic. the recommended power supply control guidelines are that the commercial frequency (50 to 60 hz) ripple variation (p-p value) on v cc should be less than 10% of the standard v cc value and that the transient rate of change during sudden changes, such as during power supply switching, should be less than 0.1 v/ms. 7. notes on using an external clock when using an external clock, drive the x0 pin as illustrated below. when an external clock is used, oscillation stabilization time is required even for power-on reset and wake-up from stop mode. x0 x1 mb90210 note: when using an external clock, be sure to input external clock more than 6 machine cycles after setting the hst pin to ??to transfer to the hardware standby mode. use of external clock
mb90210 series 18 8. power-on sequence for a/d converter power supplies and analog inputs be sure to turn on the digital power supply (v cc ) before applying voltage to the a/d converter power supplies (av cc , avrh, and avrl) and analog inputs (an0 to an7). when turning power supplies off, turn off the a/d converter power supplies (av cc , avrh, and avrl) and analog inputs (an0 to an7) first, then the digital power supply (v cc ). when turning avrh on or off, be careful not to let it exceed av cc .
19 mb90210 series n programming for MB90P214A/p214b/w214a/w214b in eprom mode, the MB90P214A/p214b/w214a/w214b functions equivalent to the mbm27c1000. this allows the eprom to be programmed with a general-purpose eprom programmer by using the dedicated socket adapter (do not use the electronic signature mode). 1. program mode when shipped from fujitsu, and after each erasure, all bits (64 k 8 bits) in the MB90P214A/p214b/w214a/ w214b are in the 1 state. data is written to the rom by selectively programming 0s into the desired bit locations. bits cannot be set to 1 electrically. 2. programming procedure (1) set the eprom programmer to mbm27c1000. (2) load program data into the eprom programmer at 10000 h to 1ffff h . note that rom addresses ff0000 h to ffffff h in the operation mode in the MB90P214A/p214b/w214a/ w214b series assign to 10000 h to 1ffff h in the eprom mode (on the eprom programmer). (3) mount the MB90P214A/p214b/w214a/w214b on the adapter socket, then fit the adapter socket onto the eprom programmer. when mounting the device and the adapter socket, pay attention to their mounting orientations. (4) start programming the program data to the device. (5) if programming has not successfully resulted, connect a capacitor of approx. 0.1 m f between v cc and gnd, between v pp and gnd. (6) since the MB90P214A and mb90w214a have cmos-level input, programming to them may be impossible depending on the output level of the general-purpose programmer. in that case, connect a pull-up resistor to the adapter socket side. note: the mask rom products (mb90214) does not support eprom mode. data cannot, therefore, be read by the eprom programmer. ffffff h 10000 h * 1ffff h * operation mode eprom mode (corresponding addresses on the eprom mode) ff0000 h * : be sure to set the pro g rammin g , the start address and the stop address on the eprom pro g rammer to 10000 h /1ffff h .
mb90210 series 20 3. eprom programmer socket adapter and recommended programmer manufacturer inquiry: sun hayato co., ltd.: tel: (81)-3-3986-0403 fax: (81)-3-5396-9106 advantest corp.: tel: except japan (81)-3-3930-4111 4. erase procedure data written in the mb90w214a/w214b are erased (from 0 to 1) by exposing the chip to ultraviolet rays with a wavelength of 2,537 ? through the translucent cover. recommended irradiation dosage for exposure is 10 wsec/cm 2 . this amount is reached in 15 to 20 minutes with a commercial ultraviolet lamp positioned 2 to 3 cm above the package (when the package surface illuminance is 1200 m w/cm 2 ). if the ultraviolet lamp has a filter, remove the filter before exposure. attaching a mirrored plate to the lamp increases the illuminance by a factor of 1.4 to 1.8, thus shortening the required erasure time. if the translucent part of the package is stained with oil or adhesive, transmission of ultraviolet rays is degraded, resulting in a longer erasure time. in that case, clean the translucent part using alcohol (or other solvent not affecting the package). the above recommended dosage is a value which takes the guard band into consideration and is a multiple of the time in which all bits can be evaluated to have been erased. observe the recommended dosage for erasure; the purpose of the guard band is to ensure erasure in all temperature and supply voltage ranges. in addition, check the life span of the lamp and control the illuminance appropriately. data in the mb90w214a/w214b are erased by exposure to light with a wavelength of 4000 ? or less. data in the device is also erased even by exposure to fluorescent lamp light or sunlight although the exposure results in a much lower erasure rate than exposure to 2537 ? ultraviolet rays. note that exposure to such lights for an extended period will therefore affect system reliability. if the chip is used where it is exposed to any light with a wavelength of 4000 ? or less, cover the translucent part, for example, with a protective seal to prevent the chip from being exposed to the light. exposure to light with a wavelength of 4,000 to 5,000 ? or more will not erase data in the device. if the light applied to the chip has a very high illuminance, however, the device may cause malfunction in the circuit for reasons of general semiconductor characteristics. although the circuit will recover normal operation when exposure is stopped, the device requires proper countermeasures for use in a place exposed continuously to such light even though the wavelength is 4,000 ? or more. part no. mb90p214b package qfp-80 compatible socket adapter sun hayato co., ltd. rom-80qf-32dp-16f recommended programmer manufacturer and programmer name advantest corp. r4945a (main unit) + r49451a (adapter) recommended
21 mb90210 series 5. recommended screening conditions high temperature aging is recommended as the pre-assembly screening procedure. 6. programming yeild MB90P214A/p214b cannot be write-tested for all bits due to their nature. therefore the write yield cannot always be guaranteed to be 100%. 7. pin assignment in eprom mode (1) pins compatible with mbm27c1000 mbm27c1000 MB90P214A, mb90p214b, mb90w214a, mb90w214b mbm27c1000 MB90P214A, mb90p214b, mb90w214a, mb90w214b pin no. pin name pin no. pin name pin no. pin name pin no. pin name 1v pp 43 md2 (v pp )32 v cc 2 oe 59 p55 31 pgm 60 p56 3a1519p37 30n.c. 4 a12 16 p34 29 a14 18 p36 5 a07 10 p27 28 a13 17 p35 6 a06 9 p26 27 a08 12 p30 7 a05 8 p25 26 a09 13 p31 8 a04 7 p24 25 a11 15 p33 9 a03 6 p23 24 a16 20 p40 10 a02 5 p22 23 a10 14 p32 11 a01 4 p21 22 ce 58 p54 12 a00 3 p20 21 d07 74 p07 13 d00 67 p00 20 d06 73 p06 14 d01 68 p01 19 d05 72 p05 15 d02 69 p02 18 d04 71 p04 16 gnd 17 d03 70 p03 program, verify aging +150 c, 48 hrs. data verification assembly
mb90210 series 22 (2) power supply and ground connection pins (3) pins other than mbm27c1000-compatible pins type pin no. pin name power supply 41 42 44 66 md0 md1 hst v cc gnd 11 30 31 34 56 57 62 63 v ss avrl av ss v ss p52 p53 rst v ss pin no. pin name treatment 64 x0 pull up to 4.7 k w . 65 x1 open 1 2 21 to 27 28 29 32 33 35 to 40 45 to 50 51 to 53 54 55 61 75 to 80 p16 p17 p41 to p47 av cc avrh p60 p61 p62 to p67 p70 to p75 p80 to p82 p50 p51 p57 p10 to p15 connect a pull-up resistor of approximately 1 m w to each pin.
23 mb90210 series n block diagram 4 uart 3 pwc timer 4 16-bit timer 1 4 dtp/external interrupt 4 external bus interface 16-bit timer 2 4 f 2 mc-16f cpu ram rom 10-bit a/d converter 8 ch. cts0 sck3 sid3 sod3 sck2 sid2 sod2 sck1 sid1 sod1 sck0 sid0 sod0 tout0 to tout3 tin0 to tin3 atg an0 to an7 av cc avrh avrl av ss pwc0 to pwc3 /pout0 to pout3 int0 to int3 d00 to d15 a00 to a23 clk rdy hak hrq wrh wrl rd tin4 to tin7 internal data bus 8-bit ppg timer ppg 8-bit ppg timer p00 to p07 p10 to p17 p20 to p27 p30 to p37 p40 to p47 p50 to p57 p60 to p67 p70 to p75 p80 to p82 8-bit ppg timer i/o port 13 65 write-inhibit ram wi clock controller x1 x0 rst hst md2 md1 md0 7 8 13 4 4 4 47
mb90210 series 24 n programming model accumulator user stack pointer system stack pointer processor status program counter user stack upper register system stack upper register user stack lower register system stack lower register direct page register program bank register data bank register user stack bank register system stack bank register additional data bank register max.32 banks rw 7 rw 6 rw 5 rw 4 r 7 r 5 r 3 r 1 r 6 r 4 r 2 r 0 rw3 rw 2 rw 1 rw 0 rl 3 rl 2 rl 1 rl 0 000180 h + rp 10 h ilm istnzvc processor status (ps) general-purpose registers dedicated registers ah al usp ssp ps pc uspcu sspcu uspcl sspcl dpr pcb dtb usb ssb adb 8 bits 16 bits 32 bits c c r 16 bits msb lsb rp upper lower
25 mb90210 series n memory map single chip internal rom and external bus external rom and external bus ffffff h address #1 010000 h address #2 address #4 address #5 address #6 peripherals ram registers ram ram write-inhibit ram rom area ff bank image rom area rom area 000380 h 000180 h 0000c0 h 000000 h 000100 h : internal : external : no access rom area ff bank image write-inhibit ram write-inhibit ram registers registers peripherals peripherals address #3 type address #1 address #2 address #3 address #4 address #5 address #6 mb90214 ff0000 h 004000 h 001300 h 001200 h 001100 h 000d00 h MB90P214A/p214b mb90w214a/w214b ff0000 h 004000 h 001300 h 001200 h 001100 h 001100 h mb90v210 (fe0000 h ) 004000 h 001300 h 001300 h 001100 h 001100 h
mb90210 series 26 n i/o map (continued) address register register name access resource name initial value 000000 h * 3 port 0 data register pdr0 r/w port 0 xxxxxxxx 000001 h * 3 port 1 data register pdr1 r/w port 1 xxxxxxxx 000002 h * 3 port 2 data register pdr2 r/w port 2 xxxxxxxx 000003 h * 3 port 3 data register pdr3 r/w port 3 xxxxxxxx 000004 h * 3 port 4 data register pdr4 r/w port 4 xxxxxxxx 000005 h * 3 port 5 data register pdr5 r/w port 5 xxxxxxxx 000006 h port 6 data register pdr6 r/w port 6 11111111 000007 h port 7 data register pdr7 r/w port 7 C C xxxxxx 000008 h port 8 data register pdr8 r/w port 8 CCC CC xx x 000009 h to 0f h (reserved area) * 1 000010 h * 3 port 0 data direction register ddr0 r/w port 0 00000000 000011 h * 3 port1 data direction register ddr1 r/w port 1 00000000 000012 h * 3 port 2 data direction register ddr2 r/w port 2 00000000 000013 h * 3 port 3 data direction register ddr3 r/w port 3 00000000 000014 h * 3 port 4 data direction register ddr4 r/w port 4 00000000 000015 h * 3 port 5 data direction register ddr5 r/w port 5 00000000 000016 h analog input enable register ader r/w port 6 11111111 000017 h port 7 data direction register ddr7 r/w port 7 C C 0 00 00 0 000018 h port 8 data direction register ddr8 r/w port 8 C C C C C 0 00 000019 h to 1f h (reserved area) * 1 000020 h mode control register 0 umc0 r/w uart (ch.0) 00000100 000021 h status register 0 usr0 r/w 00010000 000022 h input data register 0/output data register 0 uidr0/ uodr0 r/w xxxxxxxx 000023 h rate and data register 0 urd0 r/w 0 0000000 000024 h mode control register 1 umc1 r/w uart (ch.1) 00000100 000025 h status register 1 usr1 r/w 00010000 000026 h input data register 1/output data register 1 uidr1/ uodr1 r/w xxxxxxxx 000027 h rate and data register 1 urd1 r/w 0 0000000
27 mb90210 series (continued) address register register name access resource name initial value 000028 h mode control register 2 umc2 r/w uart (ch.2) 00000100 000029 h status register 2 usr2 r/w 00010000 00002a h input data register 2/output data register 2 uidr2/ uodr2 r/w xxxxxxxx 00002b h rate and data register 2 urd2 r/w 0 0 0 0 0 0 0 0 00002c h uart redirect control register urdr r/w uart (ch.0/2) C C C 0 0000 00002d h to 2f h (reserved area) * 1 000030 h interrupt/dtp enable register enir r/w dtp/external interrupt CCCC0000 000031 h interrupt/dtp factor register eirr r/w C C C C 0000 000032 h request level setting register elvr r/w 00000000 000033 h (reserved area) * 1 000034 h ad control status register adcs r/w 10-bit a/d converter 00000000 000035 h 00000000 000036 h to 37 h ad data register adcd r/w *4 xxxxxxxx 0CCCCCxx 000038 h to 39 h timer control status register 0 tmcsr0 r/w 16-bit reload timer 1 (ch.0) 00000000 CCCC0000 00003a h to 3b h timer control status register 1 tmcsr1 r/w 16-bit reload timer 1 (ch.1) 00000000 CCCC0000 00003c h to 3d h timer control status register 2 tmcsr2 r/w 16-bit reload timer 1 (ch.2) 00000000 CCCC0000 00003e h to 3f h timer control status register 3 tmcsr3 r/w 16-bit reload timer 1 (ch.3) 00000000 CCCC0000 000040 h timer 0 timer register tmr0 r 16-bit reload timer 1 (ch.0) xxxxxxxx 000041 h xxxxxxxx 000042 h timer 0 reload register tmrlr0 w xxxxxxxx 000043 h xxxxxxxx 000044 h timer 1 timer register tmr1 r 16-bit reload timer 1 (ch.1) xxxxxxxx 000045 h xxxxxxxx 000046 h timer 1 reload register tmrlr1 w xxxxxxxx 000047 h xxxxxxxx
mb90210 series 28 (continued) address register register name access resource name initial value 000048 h timer 2 timer register tmr2 r 16-bit reload timer 1 (ch.2) xxxxxxxx 000049 h xxxxxxxx 00004a h timer 2 reload register tmrlr2 w xxxxxxxx 00004b h xxxxxxxx 00004c h timer 3 timer register tmr3 r 16-bit reload timer 1 (ch.3) xxxxxxxx 00004d h xxxxxxxx 00004e h timer 3 reload register tmrlr3 w xxxxxxxx 00004f h xxxxxxxx 000050 h timer 4 timer register tmr4 r 16-bit reload timer 2 (ch.4) xxxxxxxx 000051 h xxxxxxxx 000052 h timer 4 reload register tmrlr4 w xxxxxxxx 000053 h xxxxxxxx 000054 h timer 5 timer register tmr5 r 16-bit reload timer 2 (ch.5) xxxxxxxx 000055 h xxxxxxxx 000056 h timer 5 reload register tmrlr5 w xxxxxxxx 000057 h xxxxxxxx 000058 h timer 6 timer register tmr6 r 16-bit reload timer 2 (ch.6) xxxxxxxx 000059 h xxxxxxxx 00005a h timer 6 reload register tmrlr6 w xxxxxxxx 00005b h xxxxxxxx 00005c h timer 7 timer register tmr7 r 16-bit reload timer 2 (ch.7) xxxxxxxx 00005d h xxxxxxxx 00005e h timer 7 reload register tmrlr7 w xxxxxxxx 00005f h xxxxxxxx 000060 h timer control status register 4 tmcsr4 r/w 16-bit reload timer 2 (ch.4) 00000000 000061 h (reserved area) * 1 000062 h timer control status register 5 tmcsr5 r/w 16-bit reload timer 2 (ch.5) 00000000 000063 h (reserved area) * 1 000064 h timer control status register 6 tmcsr6 r/w 16-bit reload timer 2 (ch.6) 00000000 000065 h (reserved area) * 1
29 mb90210 series (continued) address register register name access resource name initial value 000066 h timer control status register 7 tmcsr7 r/w 16-bit reload timer 2 (ch.7) 00000000 000067 h (reserved area) * 1 000068 h pwc0 divide ratio register divr0 r/w pwc timer (ch.0) CCCCCC00 000069 h (reserved area) * 1 00006a h pwc1 divide ratio register divr1 r/w pwc timer (ch.1) CCCCCC00 00006b h (reserved area) * 1 00006c h pwc2 divide ratio register divr2 r/w pwc timer (ch.2) CCCCCC00 00006d h (reserved area) * 1 00006e h pwc3 divide ratio register divr3 r/w pwc timer (ch.3) CCCCCC00 00006f h (reserved area) * 1 000070 h pwc0 control status register pwcsr0 r/w pwc timer (ch.0) 00000000 000071 h 00000000 000072 h pwc0 data buffer register pwcr0 r/w 00000000 000073 h 00000000 000074 h pwc1 control status register pwcsr1 r/w pwc timer (ch.1) 00000000 000075 h 00000000 000076 h pwc1 data buffer register pwcr1 r/w 00000000 000077 h 00000000 000078 h pwc2 control status register pwcsr2 r/w pwc timer (ch.2) 00000000 000079 h 00000000 00007a h pwc2 data buffer register pwcr2 r/w 00000000 00007b h 00000000 00007c h pwc3 control status register pwcsr3 r/w pwc timer (ch.3) 00000000 00007d h 00000000 00007e h pwc3 data buffer register pwcr3 r/w 00000000 00007f h 00000000 000080 h to 87 h (reserved area) * 1 000088 h ppg operation mode control register ppgc r/w 8-bit ppg timer 00000CC1 000089 h (reserved area) * 1
mb90210 series 30 (continued) address register register name access resource name initial value 00008a h ppg reload register prl r/w 8-bit ppg timer xxxxxxxx 00008b h xxxxxxxx 00008c h to 8d h (reserved area) * 1 00008e h wi control register wicr r/w write-inhibit ram CCCxCCCC 00008f h to 9e h (reserved area) * 1 00009f h delayed interrupt source generate/ release register dirr r/w delayed interrupt generation module CCCCCCC0 0000a0 h standby control register stbyc r/w low-power consumption mode 0001 **** 0000a1 h to a2 h (reserved area) * 1 0000a3 h middle address control register macr w external pin ######## 0000a4 h upper address control register hacr w ######## 0000a5 h external pin control register epcr w ##0C0#00 0000a6 h to a7 h (reserved area) * 1 0000a8 h watchdog timer control register wtc r/w watchdog timer xxxxxxxx 0000a9 h timebase timer control register tbtc r/w timebase timer 1 C C0 0 00 0 0000aa h to af h (reserved area) * 1 0000b0 h interrupt control register 00 icr00 r/w interrupt controller 00000111 0000b1 h interrupt control register 01 icr01 r/w 0 0 00 0 11 1 0000b2 h interrupt control register 02 icr02 r/w 0 0 00 0 11 1 0000b3 h interrupt control register 03 icr03 r/w 0 0 00 0 11 1 0000b4 h interrupt control register 04 icr04 r/w 0 0 00 0 11 1 0000b5 h interrupt control register 05 icr05 r/w 0 0 00 0 11 1 0000b6 h interrupt control register 06 icr06 r/w 0 0 00 0 11 1 0000b7 h interrupt control register 07 icr07 r/w 0 0 00 0 11 1 0000b8 h interrupt control register 08 icr08 r/w 0 0 00 0 11 1 0000b9 h interrupt control register 09 icr09 r/w 0 0 00 0 11 1
31 mb90210 series (continued) initial value 0: the initial value of this bit is 0. 1: the initial value of this bit is 1. x: the initial value of this bit is undefined. C: this bit is not used. the initial value is undefined. * : the initial value of this bit varies with the reset source. #: the initial value of this bit varies with the operation mode. *1: access inhibited *2: the only area available for the external access below address 0000ff h is this area. accesses to these addresses are handled as accesses to an external i/o area. *3: when the external bus is enabled, do not access any register not serving as a general-purpose port in the areas from address 000000 h to 000005 h and from 000010 h to 000015 h . *4: writing to bit 15 is possible. writing to other bits is used as a test function. address register register name access resource name initial value 0000ba h interrupt control register 10 icr10 r/w interrupt controller 00000111 0000bb h interrupt control register 11 icr11 r/w 0 0 00 0 11 1 0000bc h interrupt control register 12 icr12 r/w 0 0 00 0 11 1 0000bd h interrupt control register 13 icr13 r/w 0 0 00 0 11 1 0000be h interrupt control register 14 icr14 r/w 0 0 00 0 11 1 0000bf h interrupt control register 15 icr15 r/w 0 0 00 0 11 1 0000c0 h to ff h (external area) * 2
mb90210 series 32 n interrupt sources and interrupt vectors/interrupt control registers (continued) interrupt source ei 2 os support interrupt vector interrupt control register no. address icr address reset # 08 08 h ffffdc h int9 instruction # 09 09 h ffffd8 h exceptional # 10 0a h ffffd4 h uart interrupt #0 # 11 0b h ffffd0 h icr00 000b0 h uart interrupt #1 # 12 0c h ffffcc h uart interrupt #2 # 13 0d h ffffc8 h icr01 000b1 h uart interrupt #3 # 14 0e h ffffc4 h pwc timer # 0 count completed # 15 0f h ffffc0 h icr02 000b2 h pwc timer # 0 overflow # 16 10 h ffffbc h pwc timer # 1 count completed # 17 11 h ffffb8 h icr03 000b3 h pwc timer # 1 overflow # 18 12 h ffffb4 h pwc timer # 2 count completed # 19 13 h ffffb0 h icr04 000b4 h pwc timer # 2 overflow # 20 14 h ffffac h pwc timer # 3 count completed # 21 15 h ffffa8 h icr05 000b5 h pwc timer # 3 overflow # 22 16 h ffffa4 h 16-bit reload timer 1 # 0 overflow # 23 17 h ffffa0 h icr06 000b6 h 16-bit reload timer 1 # 1 overflow # 24 18 h ffff9c h 16-bit reload timer 1 # 2 overflow # 25 19 h ffff98 h icr07 000b7 h 16-bit reload timer 1 # 3 overflow # 26 1a h ffff94 h 16-bit reload timer 2 # 4 overflow # 27 1b h ffff90 h icr08 000b8 h 16-bit reload timer 2 # 5 overflow # 28 1c h ffff8c h 16-bit reload timer 2 # 6 overflow # 29 1d h ffff88 h icr09 000b9 h 16-bit reload timer 2 # 7 overflow # 30 1e h ffff84 h a/d converter count completed # 31 1f h ffff80 h icr10 000ba h timebase timer interval interrupt # 32 20 h ffff7c h uart2 transmission completed # 33 21 h ffff78 h icr11 000bb h uart2 reception completed # 34 22 h ffff74 h
33 mb90210 series (continued) :ei 2 os is supported (with stop request). :ei 2 os is supported; however, since two interrupt sources are allocated to a single icr, in case ei 2 os is used for one of the two, ei 2 os and ordinary interrupt are not both available for the other (with stop request). :ei 2 os is supported; however, since two interrupt sources are allocated to a single icr, in case ei 2 os is used for one of the two, ei 2 os and ordinary interrupt are not both available for the other (with no stop request). :ei 2 os is not supported. interrupt source ei 2 os support interrupt vector interrupt control register no. address icr address uart1 transmission completed # 35 23 h ffff70 h icr12 0000bc h uart1 reception completed # 36 24 h ffff6c h uart0 transmission completed # 37 25 h ffff68 h icr13 0000bd h uart0 reception completed # 39 27 h ffff60 h icr14 0000be h delayed interrupt generation module # 42 2a h ffff54 h icr15 0000bf h stack fault # 255 ff h fffc00 h
mb90210 series 34 n peripheral resources 1. parallel ports the mb90210 series has 57 i/o pins and 8 open-drain i/o pins. ports 0 to 5, 7, and 8 are i/o ports. each of these ports serves as an input port when the data direction register value is 0 and as an output port when the value is 1. port 6 is an open-drain port, which may be used as a port when the analog input enable register value is 0. (1) register configuration port data registers 0 to 8 (pdr0 to pdr8) port direction registers 0 to 5, 7, and 8 (ddr0 to ddr5, ddr7, and ddr8) 000001 h 000003 h 000005 h 000007 h pdr1 pdr3 pdr5 pdr7 address: port data register 000000 h 000002 h 000004 h 000006 h 000008 h pdr0 pdr2 pdr4 pdr6 pdr8 address: port data register 15 14 13 12 11 10 9 8 76543210 bit bit pdx7 pdx0 pdx1 pdx2 pdx3 pdx4 pdx5 pdx6 pdx7 pdx0 pdx1 pdx2 pdx3 pdx4 pdx5 pdx6 pdrx ? only for the pdr6 note: no re g ister bit is included in bits 7 and 6 of port 7 or bits 7 to 3 of port 8. (r/w) (x) (r/w) (x) (r/w) (x) (r/w) (x) (r/w) (x) (r/w) (x) (r/w) (x) (r/w) (x) (r/w) (x) (1) (r/w) (x) (1) (r/w) (x) (1) (r/w) (x) (1) (r/w) (x) (1) (r/w) (x) (1) (r/w) (x) (1) (r/w) (x) (1) read/write initial value read/write initial value ? ? ? ? 000011 h 000013 h 000015 h 000017 h ddr1 ddr3 ddr5 ddr7 address: port direction register 000010 h 000012 h 000014 h 000018 h ddr0 ddr2 ddr4 ddr8 address: port direction register 15 14 13 12 11 10 9 8 76543210 bit bit ddx7 ddx0 ddx1 ddx2 ddx3 ddx4 ddx5 ddx6 ddx7 ddx0 ddx1 ddx2 ddx3 ddx4 ddx5 ddx6 ddrx no register bit is included in bits 7 and 6 of port 7 or bits 7 to 3 of port 8. port 6 has no ddr. note: (r/w) (0) (r/w) (0) (r/w) (0) (r/w) (0) (r/w) (0) (r/w) (0) (r/w) ( 0) (r/w) (0) (r/w) (0) (r/w) (0) (r/w) (0) (r/w) (0) (r/w) (0) (r/w) (0) (r/w) (0) (r/w) (0) read/write initial value read/write initial value ? ? ? ?
35 mb90210 series (2) block diagram analog input enable register (ader) 000016 h ader address: analog input enable register 76543210 bit ade7 ade0 ade1 ade2 ade3 ade4 ade5 ade6 ader (r/w) (1) (r/w) (1) (r/w) (1) (r/w) (1) (r/w) (1) (r/w) (1) (r/w) (1) (r/w) (1) read/write initial value ? ? port data register read port data register write port direction register write port direction register read port data register port direction register pin port data register read port data register write analog input enable register write analog input enable register read port data register analog input enable register pin rmw (read-modify-write instruction) internal data bus internal data bus i/o port (port 0 to 5, 7, and 8) i/o port with an open-drain output (port 6)
mb90210 series 36 2. 16-bit reload timer 1 (with event count function) the 16-bit reload timer 1 consists of a 16-bit down counter, a 16-bit reload register, an input pin (tin), an output pin (tout), and a control register. the input clock can be selected from among three internal clocks and one external clock. at the output pin (tout), the pulses in the toggled output waveform are output in the reload mode; the rectangular pulses indicating that the timer is counting are in the single-shot mode. the input pin (tin) can be used for event input in the event count mode, and for trigger input or gate input in the internal clock mode. mb90210 series contains four channels for this timer. (1) register configuration timer control status register (tmcsr) timer register (tmr) 000039 h 00003b h 00003d h 00003f h ch.0 ch.1 ch.2 ch.3 address: timer control status register (upper byte) 000038 h 00003a h 00003c h 00003e h ch.0 ch.1 ch.2 ch.3 address: timer control status register (lower byte) 15 14 13 12 11 10 9 8 76543210 bit bit mdo0 trg cnte uf inte reld outl oute mod1 mod2 csl0 csl1 tmcsrx ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) (r/w) (0) (r/w) (0) (r/w) (0) (r/w) (0) (r/w) (0) (r/w) (0) (r/w) (0) (r/w) (0) (r/w) (0) (r/w) (0) (r/w) (0) (r/w) (0) read/write initial value read/write initial value ? ? ? ? 000041 h 000045 h 000049 h 00004d h ch.0 ch.1 ch.2 ch.3 address: timer register (upper byte) 000040 h 000044 h 000048 h 00004c h ch.0 ch.1 ch.2 ch.3 address: timer register (lower byte) 15 14 13 12 11 10 9 8 76543210 bit bit tmrx ( r ) (x) ( r ) (x) ( r ) (x) ( r ) (x) ( r ) (x) ( r ) (x) ( r ) (x) ( r ) (x) ( r ) (x) ( r ) (x) ( r ) (x) ( r ) (x) ( r ) (x) ( r ) (x) ( r ) (x) ( r ) (x) read/write initial value read/write initial value ? ? ? ?
37 mb90210 series (2) block diagram reload register (tmrlr) 000043 h 000047 h 00004b h 00004f h ch.0 ch.1 ch.2 ch.3 address: reload register (upper byte) 000042 h 000046 h 00004a h 00004e h ch.0 ch.1 ch.2 ch.3 address: reroal register (lower byte) 15 14 13 12 11 10 9 8 76543210 bit bit tmrlrx ( w ) (x) ( w ) (x) ( w ) (x) ( w ) (x) ( w ) (x) ( w ) (x) ( w ) (x) ( w ) (x) ( w ) (x) ( w ) (x) ( w ) (x) ( w ) (x) ( w ) (x) ( w ) (x) ( w ) (x) ( w ) (x) read/write initial value read/write initial value ? ? ? ? 16 8 16 16-bit reload register internal data bus 16-bit down counter reload uf 2 gate out ctl. 2 clock selector csl 1 csl 0 retrigger in ctl exck 3 prescaler clear mod 2 mod 1 mod 0 reld oute outl i nte uf cnte trg ei osclr irq clear 2 port (tin) port (tout) uart (timer 1 ch.2 output) a/d (timer 1 ch.3 output) internal clock ff f 22 2 13 5 2 3
mb90210 series 38 3. 16-bit reload timer 2 (with gate mode) the 16-bit reload timer 2 consists of a 16-bit down counter, a 16-bit reload register, an input pin (tin), and an 8-bit control register. the input clock can be selected from among four internal clocks. the mb90210 series contains four channels for this timer. (1) register configuration timer control status register (tmcsr) timer register (tmr) reload register (tmrlr) 000060 h 000062 h 000064 h 000066 h ch.4 ch.5 ch.6 ch.7 address: timer control status register 76543210 bit csl1 strt uf inte reld gatl gate csl0 tmcsrx (r/w) (0) (r/w) (0) (r/w) (0) (r/w) (0) (r/w) (0) (r/w) (0) (r/w) (0) (r/w) (0) read/write initial value ? ? 000051 h 000055 h 000059 h 00005d h ch.4 ch.5 ch.6 ch.7 address: timer register (upper byte) 000050 h 000054 h 000058 h 00005c h ch.4 ch.5 ch.6 ch.7 address: timer register (lower byte) 15 14 13 12 11 10 9 8 76543210 bit bit tmrx ( r ) (x) ( r ) (x) ( r ) (x) ( r ) (x) ( r ) (x) ( r ) (x) ( r ) (x) ( r ) (x) ( r ) (x) ( r ) (x) ( r ) (x) ( r ) (x) ( r ) (x) ( r ) (x) ( r ) (x) ( r ) (x) read/write initial value read/write initial value ? ? ? ? 000053 h 000057 h 00005b h 00005f h ch.4 ch.5 ch.6 ch.7 address: reload register (upper byte) 000052 h 000056 h 00005a h 00005e h ch.4 ch.5 ch.6 ch.7 address: reload register (lower byte) 15 14 13 12 11 10 9 8 76543210 bit bit tmrlrx ( w ) (x) ( w ) (x) ( w ) (x) ( w ) (x) ( w ) (x) ( w ) (x) ( w ) (x) ( w ) (x) ( w ) (x) ( w ) (x) ( w ) (x) ( w ) (x) ( w ) (x) ( w ) (x) ( w ) (x) ( w ) (x) read/write initial value read/write initial value ? ? ? ?
39 mb90210 series (2) block diagram csl 1 csl 0 clock selector 16-bit down counter internal data bus uf 16-bit reload register reload port (tin) in ctl irq ffff 22 2 256 2 8 reld inte uf strt clear (reld = 0) 2 gate gatl 2 2 16 4 16 2 gate ei osclr 2 clear
mb90210 series 40 4. uart the uart is a serial i/o port for synchronous or asynchronous communication with external resources. it has the following features: ? full duplex double buffer ? data transfer synchronous or asynchronous with clock pulses ? multiprocessor mode support (mode 2) ? built-in dedicated baud-rate generator (nine types) ? arbitrary baud-rate setting from external clock input or internal timer (use the 16-bit reroad timer 1 channel 2 for internal timer.) ? variable data length (7 to 9 bits (without parity bit); 6 to 8 bits (with parity bit)) ? variable data length (7 to 9 bit no parity, 6 to 8 bit with parity) ? error detection function (framing, overrun, parity) ? interrupt function (two sources for transmission and reception) ? transfer in nrz format the mb90210 series contains three channels for the uart. uart channel 0 has the cts function. uart channel 2 provides dual i/o pin switching. (1) register configuration 000021 h 000025 h 000029 h ch.0 ch.1 ch.2 address: status register 000022 h 000026 h 00002a h ch.0 ch.1 ch.2 address: input data register/output data register 15 14 13 12 11 10 9 8 76543210 bit bit d7 d0 d1 d2 d3 d4 d5 d6 rdrf tbf rbf tie rie tdre pe orfe uidr (read)/ uodr (write) usr (r) (0) (r) (0) (r) (0) (r) (1) (r/w) (0) (r) (0) (r) (0) (r/w) (0) (r/w) (x) (r/w) (x) (r/w) (x) (r/w) (x) (r/w) (x) (r/w) (x) (r/w) (x) (r/w) (x) read/write initial value read/write initial value ? ? ? ? 000020 h 000024 h 000028 h ch.0 ch.1 ch.2 address: serial mode control register 76543210 bit pen soe scke rfc smde mc0 mc1 sbl umc (r/w) (0) (r/w) (0) (r/w) (0) (r/w) (0) (r/w) (0) (r/w) (0) (r/w) (0) (w) (1) read/write initial value ? ? status register (usr) serial mode control register (umc) input data register (uidr)/output data register (uodr)
41 mb90210 series 000023 h 000027 h 00002b h ch.0 ch.1 ch.2 address: rate and data register 00002c h address: uart redirect control register 15 14 13 12 11 10 9 8 76543210 bit bit sel3 udpe ctse csp cte bch d8 p bch0 rc0 rc1 rc2 rc3 urdr urdx (r/w) (0) (r/w) (0) (r/w) (0) (r/w) (0) (r/w) (0) (r/w) (0) (r/w) (0) (r/w) (0) (? (? (? (? (? (? (r/w) (0) (r/w) (0) (r/w) (0) (r/w) (0) (r/w) (0) read/write initial value read/write initial value ? ? ? ? rate and data register (urd) uart redirect control register (urdr)
mb90210 series 42 (2) block diagram control bus dedicated baud-rate clock external clock 16-bit reload timer 1 channel 2 (internally connected) clock selector circuit receiving clock pulse transmitting clock pulse reception interrupt (to cpu) sck0 to sck3 transmission interrupt (to cpu) transmission control circuit sod0 to sod3 transmission shifter uodr start of transmission reception control circuit start bit detector transmission control circuit transmission bit counter transmission parity counter received bit counter recieved parity bit counter reception shifter internal data bus end of reception sidr reception error occurence signal for ei 2 os (to cpu) reception status detection circuit umc register usr register urd register pen sbl mc1 mc0 smde rfc scke soe rdrf orfe pe tdre rie tie rbf tbf bch rc3 rc2 rc1 rc0 bch0 p d8 control bus sid0 to sid3
43 mb90210 series 5. 10-bit a/d converter the 10-bit a/d converter converts the analog input voltage to a digital value. it has the following features: ? conversion time: min.6.125 m s per channel (at 16-mhz machine clock) ? rc-type successive approximation with built-in sample-and-hold circuit ? 10-bit or 8-bit resolution ? eight analog input channels programmable for selection single conversion mode: selects and converts one channel. scan conversion mode: converts multiple consecutive channels (up to eight channels programmable). consecutive conversion mode: converts a specified channel repeatedly. stop conversion mode: converts one channel and suspends its own operation until the next activation (allowing synchronized conversion start). ? on completion of a/d conversion, the converter can generate an interrupt request to the cpu. this interrupt generation can activate the ei 2 os to transfer the a/d conversion result to memory, making the converter suitable for continuous operation. ? conversion can be activated by software, external trigger (falling edge), and/or timer (rising edge) as selected. use the 16-bit reroad timer 1 channel 3 for the timer. (1) register configuration 000035 h address: a/d control status register (upper byte) 000034 h address: a/d control status register (lower byte) 15 14 13 12 11 10 9 8 76543210 bit bit md1 ane0 ane1 ane2 ans0 ans1 ans2 md0 busy strt sts0 sts1 paus inte int adcs0 adcs1 (r/w) (0) (r/w) (0) (r/w) (0) (r/w) (0) (r/w) (0) (w) (0) (? (0) (r/w) (0) (r/w) (0) (r/w) (0) (r/w) (0) (r/w) (0) (r/w) (0) (r/w) (0) (r/w) (0) (r/w) (0) read/write initial value read/write initial value ? ? ? ? 000037 h address: a/d data register (upper byte) 000036 h address: a/d data register (lower byte) 15 14 13 12 11 10 9 8 76543210 bit bit d7 d0 d1 d2 d3 d4 d5 d6 s10 d8 d9 adcd0 adcd1 (w) (0) (? (? (? (? (? (? (? (? (r) (x) (r) (x) (? (? (r) (x) (r) (x) (r) (x) (r) (x) (r) (x) (r) (x) (r) (x) (r) (x) read/write initial value read/write initial value ? ? ? ? a/d control status register (adcs1 and adcs0) a/d data registers (adcd1 and adcd0)
mb90210 series 44 (2) block diagram av cc avrh/avrl av ss d/a converter internal data bus successive approximation register comparator sample-and-hold circuit mpx an0 an1 an2 an3 an4 an5 an6 an7 a/d data register adcd0, adcd1 decorder a/d control status register operation clock trigger activation timer activation 16-bit reload timer 1 channel 3 (internally connected) machine clock ( f ) prescaler atg adcs0, adcs1 input circuit
45 mb90210 series 6. pwc(pulse width count) timer the pwc (pulse width count) timer is a 16-bit multifunction up-count timer with an input-signal pulse-width count function and a reload timer function. the hardware configuration of this module is a 16-bit up-count timer, an input pulse divider with divide ratio control register, four count input pins, and a 16-bit control register. using these components, the pwc timer provides the following features: ? timer functions: an interrupt request can be generated at set time intervals. pulse signals synchronized with the timer cycle can be output. the reference internal clock can be selected from among three internal clocks. ? pulse-width count functions: the time between arbitrary pulse input events can be counted. the reference internal clock can be selected from among three internal clocks. various count modes: h pulse width ( - to ) /l pulse width ( - to ) rising-edge cycle ( - to - ) /falling-edge cycle ( to ) count between edges ( - or to or - ) cycle count can be performed by 22n division (n = 1, 2, 3, 4) of the input pulse, with an 8 bit input divider. an interrupt request can be generated once counting has been performed. the number of times counting is to be performed (once or subsequently) can be selected. the mb90210 series contains four channels for the pwc timer. (1) register configuration pwc control status register (pwcsr) 000071 h 000075 h 000079 h 00007d h ch.0 ch.1 ch.2 ch.3 address: pwc control status register (upper byte) 000070 h 000074 h 000078 h 00007c h ch.0 ch.1 ch.2 ch.3 address: pwc control status register (lower byte) 15 14 13 12 11 10 9 8 76543210 bit bit cks1 mod0 mod1 mod2 s/c pis0 pis1 cks0 strt pout err ovie ovir edie edir stop pwcsrx (r/w) (0) (r/w) (0) (r) (0) (r/w) (0) (r/w) (0) (r) (0) (r/w) (0) (r/w) (0) (r/w) (0) (r/w) (0) (r/w) (0) (r/w) (0) (r/w) (0) (r/w) (0) (r/w) (0) (r/w) (0) read/write initial value read/write initial value ? ? ? ?
mb90210 series 46 000073 h 000077 h 00007b h 00007f h ch.0 ch.1 ch.2 ch.3 address: pwc data buffer register (upper byte) 000072 h 000076 h 00007a h 00007e h ch.0 ch.1 ch.2 ch.3 address: pwc data buffer register (lower byte) 15 14 13 12 11 10 9 8 76543210 bit bit pwcr (r/w) (0) (r/w) (0) (r/w) (0) (r/w) (0) (r/w) (0) (r/w) (0) (r/w) (0) (r/w) (0) (r/w) (0) (r/w) (0) (r/w) (0) (r/w) (0) (r/w) (0) (r/w) (0) (r/w) (0) (r/w) (0) read/write initial value read/write initial value ? ? ? ? 000068 h 00006a h 00006c h 00006e h ch.0 ch.1 ch.2 ch.3 address: divide ratio control register 76543210 bit div0 div1 divr (? (? (? (? (? (? (? (? (? (? (r/w) (0) (r/w) (0) (? (? read/write initial value ? ? pwc data buffer register (pwcr) pwc divide ratio control register (divr)
47 mb90210 series (2) block diagram clock divider internal clock (machine clock/4) 2 3 2 2 cks 1 cks 0 divider clear pis 1 pis 0 pwc0 pwc1 pwc2 pwc3 f.f. pout * overflow divide ratio select divr 2 15 pwcsr channel pout pin * : the pout pins of the mb90210 series are assigned as follows: count edge end count end interrupt edge overflow interrupt request control bit output flag setting, etc. edge detection count start edge err pis 1 pis 0 cks 1 cks 0 8-bit divider dividing on/off end edge select start edge select control circuit internal data bus 16-bit up-count timer ch.0 ch.1 ch.2 ch.3 pwc pwc pwc pwc p44/a20/pwc0/pout0 p45/a21/pwc1/pout1 p46/a22/pwc2/pout2 p47/a23/pwc3/pout3 16 error detection write enable pwcr 16 16 16 timer clear count enable clock overflow data transfer reload err pwcr read
mb90210 series 48 7. 8-bit ppg timer this block is an 8-bit reload timer module for ppg output by controlling pulse output according to the timer operation. the hardware configuration of this block is an 8-bit down counter, two 8-bit reload registers, an 8-bit control register, and an external pulse output pin. using these components, the module provides the following features: ppg output operation: the module outputs pulse waves of any period and duty factor. it can also be used as a d/a converter using an external circuit. (1) register configuration 00008b h address: ppg reload register 00008a h address: ppg reload register 15 14 13 12 11 10 9 8 76543210 bit bit prll prlh (r/w) (x) (r/w) (x) (r/w) (x) (r/w) (x) (r/w) (x) (r/w) (x) (r/w) (x) (r/w) (x) (r/w) (x) (r/w) (x) (r/w) (x) (r/w) (x) (r/w) (x) (r/w) (x) (r/w) (x) (r/w) (x) read/write initial value read/write initial value ? ? ? ? 000088 h address: ppg operation mode control register 76543210 bit pen reserved puf reserved poe pcks ppgc (r/w) (0) (r/w) (0) (r/w) (0) (r/w) (0) (r/w) (0) (? (? (r/w) (1) (? (? read/write initial value ? ? ppg operation mode control register (ppgc) ppg reload registers (prll and rrlh)
49 mb90210 series (2) block diagram ppg output pin (port section) output enable output a of timebase counter output b of timebase counter ppg output latch pcnt (down counter) l/h selector invert clear pen count clock selection reload prll prlbh prlh ppgc operation mode control low-byte data bus high-byte data bus
mb90210 series 50 8. dtp/external interrupt the data transfer peripheral (dtp) is located between external peripherals and the f 2 mc-16f cpu. it receives a dma request or an interrupt request generated by the external peripherals and reports it to the f 2 mc-16f cpu to activate the extended intelligent i/o service or interrupt handler. the user can select two request levels of h and l for extended intelligent i/o service or, and four request levels of h, l, rising edge and falling edge for external interrupt requests. (1) register configuration 000030 h address: interrupt/dtp enable register 76543210 bit en0 en1 en2 en3 enir (? (? (? (? (? (? (? (? (r/w) (0) (r/w) (0) (r/w) (0) (r/w) (0) read/write initial value ? ? 000031 h address: interrupt/dtp source register 15 14 13 12 11 10 9 8 bit er0 er1 er2 er3 eirr (? (? (? (? (? (? (? (? (r/w) (0) (r/w) (0) (r/w) (0) (r/w) (0) read/write initial value ? ? 000032 h address: request level setting register 76543210 bit lb3 la0 lb0 la1 lb1 la2 lb2 la3 elvr (r/w) (0) (r/w) (0) (r/w) (0) (r/w) (0) (r/w) (0) (r/w) (0) (r/w) (0) (r/w) (0) read/write initial value ? ? interrupt/dtp enable register (enir) interrupt/dtp source register (eirr) request level setting register (elvr)
51 mb90210 series (2) block diagram interrupt/dtp enable register 4 gate internal data bus 4 source f/f edge detection circuit 4 interrupt/dtp source register 4 request level setting register 8 int
mb90210 series 52 9. watchdog timer and timebase timer the watchdog timer consists of a 2-bit watchdog counter using carry signals from an 18-bit timebase timer as the clock source, a control register, and a watchdog reset control section. the timebase timer consists of an 18- bit timer and an interval interrupt control circuit. (1) register configuration 0000a9 h address: timebase timer control register 0000a8 h address: watchdog timer control register 15 14 13 12 11 10 9 8 76543210 bit bit ponr wt0 wt1 wte srst erst wrst stbr reserved tbc0 tbc1 tbr tbof tbie wtc tbtc (w) (1) (? (? (? (? (r/w) (0) (r/w) (0) (r/w) (0) (r/w) (0) (r) (0) (r) (x) (r) (x) (r) (x) (r) (x) (r) (x) (w) (x) (w) (x) (w) (x) read/write initial value read/write initial value ? ? ? ? watchdog timer control register (wtc) timebase timer control register (tbtc)
53 mb90210 series (2) block diagram tbtc tbc1 tbc0 tbr tbie tbof selector and qr s selector timebase interrupt wtc wt1 wt0 wte ponr stbr wrst erst srst from rst bit in stbyc register rst pin from hardware standby control circuit from power-on occurence wdgrst to internal reset generator 2-bit counter internal data bus of clr watchdog reset generator clr 2 12 2 14 2 16 2 18 tbtres clock input timebase timer 2 14 2 16 2 17 2 18 oscillation clock
mb90210 series 54 10. delayed interrupt generation module the delayed interrupt generation module is used to generate an interrupt for task switching. using this module allows an interrupt request to the f 2 mc-16f cpu to generate or cancel by software. (1) register configuration (2) block diagram delayed interrupt source generate/release register (dirr) 00009f h address: delayed interrupt source generate/release register 15 14 13 12 11 10 9 8 bit r0 dirr (? (? (? (? (? (? (? (? (? (? (? (? (r/w) (0) (? (? read/write initial value ? ? delayed interrupt source generate/release register source latch internal data bus
55 mb90210 series 11. write-inhibit ram the write-inhibit ram is write-protectable with the wi pin input. maintaining the l level input to the wi pin prevents a certain area of ram from being written. the wi pin has a 4-machine-cycle filter. (1) register configuration (2) write-inhibit ram area write-inhibit ram area 001100 h to 0011ff h (mb90214/p214a/p214b/w214a/w214b) 001100 h to 0012ff h (mb90v210) (3) block diagram wi control register (wicr) 00008e h address: wi control register 76543210 bit wi wicr (? (? (? (? (? (? (r/w) (1) (? (? (? (? (? (? (? (? read/write initial value ? ? w i 4-machine-cycle skew removal 4-machine-cycle skew removal s q r access to other area internal data bus sq preceded r write-inhibit circuit select ram decoder write- inhibit ram wr l h
mb90210 series 56 12. low-power consumption modes, oscillation stabilization delay time, and gear function the mb90210 series has three low-power consumption modes: the sleep mode, the stop mode, the hardware standby mode, and gear function. sleep mode is used to suspend only the cpu operation clock; the other components remain in operation. stop mode and hardware standby mode stop oscillation, minimizing the power consumption while holding data. the clock gear function divides the external clock frequency, which is used usually as it is, to provide a lower machine clock frequency. this function can therefore lower the overall operation speed without changing the oscillation frequency. the function can select the machine clock as a division of the frequency of crystal oscillation or external clock input by 1, 2, 4, or 16. the osc1 and osc0 bits can be used to set the oscillation stabilization delay time for wake-up from stop mode or hardware standby mode. (1) register configuration standby control register (stbyc) 0000a0 h address: standby control register 76543210 bit stp clk0 clk1 osc0 osc1 rst spl slp stbyc (w) (0) (w) (0) (r/w) (0) (r/w) (1) (r/w) (*) (r/w) (*) (r/w) (*) (r/w) (*) read/write initial value ? ? note: the initial value(*) of bit0 to bit3 is changed by reset source.
57 mb90210 series (2) block diagram gear divider circuit selector 1/1 1/2 1/4 1/16 stbyc clk1 clk0 slp stp standby control circuit rst clear hst start peripheral clock generator cpu clock generator oscillation clock cpu clock peripheral clock hst pin interrupt request or rst clock input internal data bus timebase timer 2 2 2 2 2 2 2 2 0 16 17 18 14 16 17 18 selector osc1 osc0 spl rst pin high-impedance control circuit internal reset generator pin hi? rst pin internal rst to watchdog timer wdgrst
mb90210 series 58 n electrical characteristics (mb90v210, device used for evaluation, is excluded) 1. absolute maximum ratings (v ss = av ss = 0.0 v) *1: v i and v o must not exceed v cc + 0.3 v. *2: output pins p00 to p07, p10 to p17, p20 to p27, p30 to p37, p40 to p47, p50 to p57, p70 to p75, p80 to p82 *3: output pins p00 to p07, p10 to p17, p20 to p27, p30 to p37, p40 to p47, p50 to p57, p60 to p67, p70 to p75, p80 to p82 warning: semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. do not exceed these ratings. parameter symbol pin name value unit remarks min. max. power supply voltage v cc v cc v ss C 0.3 v ss + 7.0 v program voltage v pp v pp v ss C 0.3 13.0 v MB90P214A/w214a mb90p214b/w214b analog power supply voltage av cc av cc v ss C 0.3 v cc + 0.3 v power supply voltage for a/d converter avrh avrl avrh avrl v ss C 0.3 av cc v reference voltage for a/d converter input voltage v i *1 v ss C 0.3 v cc + 0.3 v output voltage v o *2 v ss C 0.3 v cc + 0.3 v l level output current i ol *3 20 ma rush current l level total output current s i ol *3 50 ma total output current h level output current i oh *2 C10 ma rush current h level total output current s i oh *2 C48 ma total output current power consumption pd 650 mw operating temperature t a C40 +105 c mb90214/p214b/w214b C40 +85 c MB90P214A/w214a storage temperature tstg C55 +150 c
59 mb90210 series 2. recommended operating conditions (v ss = av ss = 0.0 v) * : excluding the temperature rise due to the heat produced. warning: recommended operating conditions are normal operating ranges for the semiconductor device. all the devices electrical characteristics are warranted when operated within these ranges. always use semiconductor devices within the recommended operating conditions. operation outside these ranges may adversely affect reliability and could result in device failure. no warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. users considering application outside the listed conditions are advised to contact their fujitsu representative beforehand. parameter symbol pin name value unit remarks min. max. power supply voltage v cc v cc 4.5 5.5 v when operating 3.0 5.5 v retains the ram state in stop mode analog power supply voltage av cc av cc 4.5 v cc + 0.3 v power supply voltage for a/d converter avrh avrh avrl av cc v reference voltage for a/d converter avrl avrl av ss avrh v clock frequency f c 10 16mhz operating temperature t a * C40 +105 c single-chip mode mb90214/p214b/w214b C40 +85 c single-chip mode MB90P214A/w214a C40 +70 c external bus mode
mb90210 series 60 3. dc characteristics single-chip mode mb90214/p214b/w214b : (v cc = +4.5 v to +5.5 v, v ss = 0.0 v, t a = C40 c to +105 c) MB90P214A/w214a : (v cc = +4.5 v to +5.5 v, v ss = 0.0 v, t a = C40 c to +85 c) external bus mode : (v cc = +4.5 v to +5.5 v, v ss = 0.0 v, t a = C40 c to +70 c) (continued) parameter symbol pin name condition value unit remarks min. typ. max. h level input voltage v ih *1 0.7 v cc v cc + 0.3 v cmos level input v ihs *2 0.8 v cc v cc + 0.3 v hysteresis input v ihm md0 to md2 v cc C 0.3 v cc + 0.3 v l level input voltage v il *1 v ss C 0.3 0.3 v cc v cmos level input v ils *2 v ss C 0.3 0.2 v cc v hysteresis input v ilm md0 to md2 v ss C 0.3 v ss + 0.3 v h level output voltage v oh *3 v cc = 4.5 v i oh = C4.0 ma v cc C 0.5 v cc v v oh1 x1 v cc = 4.5 v i oh = C2.0 ma v cc C 2.3 v cc v l level output voltage v ol *4 v cc = 4.5 v i ol = 4.0 ma 00.4v v ol1 x1 v cc = 4.5 v i ol = 2.0 ma 0 v cc C 2.3 v input leakage current i i *1 *2 v cc =5.5 v 0.2 v cc < v i < 0.8 v cc 10 m a except pins with pull-up/pull-down resistor and rst pin i i2 x0 v cc =5.5 v 0.2 v cc < v ih < 0.8 v cc 25 m a analog power supply voltage i a av cc f c = 16 mhz 3 7 ma i ah 5* 5 m a in stop mode, t a = +25 c input capacitance c in *6 10 pf pull-up resistor r puiu rst 22 50 110 k w * 7 mb90214 MB90P214A/ w214a/p214b/ w214b md1 110 300 650 k w * 7 mb90214 generic pin 22 50 110 k w * 7 mb90214 pull-down resistor r puid md0, md2 110 300 650 k w * 7 mb90214 generic pin 22 50 110 k w * 7 mb90214
61 mb90210 series (continued) *1: cmos level input (p00 to p07, p10 to p17, x0) *2: hysteresis input pins (rst , hst , p20 to p27, p30 to p37, p40 to p47, p50 to p57, p60 to p67 p70 to p75, p80 to p82) *3: output pins (p00 to p07, p10 to p17, p20 to p27, p30 to p37, p40 to p47, p50 to p57, p70 to p75, p80 to p82) *4: output pins (p00 to p07, p10 to p17, p20 to p27, p30 to p37, p40 to p47, p50 to p57, p60 to p67, p70 to p75, p80 to p82) *5: the current value applies to the cpu stop mode with a/d converter inactive (v cc = av cc = avrh = +5.5 v). *6: other than v cc , v ss , av cc and av ss *7: a list of availabilities of pull-up/pull-down resistors *8: v cc = +5.0 v, v ss = 0.0 v, t a = +25 c, f c = 16 mhz *9: measurement condition of power supply current; external clock pin and output pin are open. measurement condition of v cc ; see the table above mentioned. parameter symbol pin name condition value unit remarks min. typ. max. power supply voltage* 9 i cc v cc f c = 16 mhz 50* 8 80 ma mb90214 70* 8 100 ma MB90P214A/ w214a mb90p214b/ w214b i ccs v cc f c = 16 mhz 40 ma in sleep mode i cch v cc 510 m a t a = +25 c in stop mode in hardware standby input time pin name mb90214 MB90P214A/w214a mb90p214b/w214b rst availability of pull-up resistors is optionally defined. pull-up resistors available pull-up resistors available md1 pull-up resistors available unavailable unavailable md0, md2 pull-down resistors available unavailable unavailable generic pin availability of pull-up/pull-down resistors is optionally defined. unavailable unavailable
mb90210 series 62 2. ac characteristics (1) clock timing standards single-chip mode mb90214/p214b/w214b : (v cc = +4.5 v to +5.5 v, v ss = 0.0 v, t a = C40 c to +105 c) MB90P214A/w214a : (v cc = +4.5 v to +5.5 v, v ss = 0.0 v, t a = C40 c to +85 c) external bus mode : (v cc = +4.5 v to +5.5 v, v ss = 0.0 v, t a = C40 c to +70 c) parameter symbol pin name condition value unit remarks min. typ. max. clock frequency f c x0, x1 10 16 mhz clock cycle time t c x0, x1 62.5 100 ns 1/f c input clock pulse width p wh p wl x0 0.4 t c 0.6 t c ns duty ratio: 60% input clock rising/falling time t cr t cf x0 8 ns t cr + t cf clock conditions clock input timings 0.7 v cc 0.7 v cc x0 0.3 v cc t cf t c t cr p wh p wl when a crystal or ceramic resonator is used when an external clock is used open x0 x1 x0 x1 c 2 c 1 c 1 = c 2 = 10 pf select the optimum capacity value for the resonator.
63 mb90210 series (2) clock output timing standards external mode: (v cc = +4.5 to +5.5 v, v ss = 0.0 v, t a = C40 c to +70 c) * : t cyc = n/f c , n gear ratio (1, 2, 4, 16) parameter symbol pin name condition value unit remarks min. typ. max. machine cycle time t cyc clk load condition: 80 pf 62.5 1600 ns * clk - ? clk t chcl t cyc / 2 C 20 t cyc /2 ns relationship between clock frequency and power supply voltage v cc [v] 5.5 4.5 016 f c [mhz] operation assurance range 10 single-chip mode external bus mode (mb90214/p214b/w214b) (MB90P214A/w214a) : (t a = ?0 c to +105 c, f c = 10 to 16 mhz) : (t a = ?0 c to +85 c, f c = 10 to 16 mhz) : (t a = ?0 c to +70 c, f c = 10 to 16 mhz) t cyc t chcl clk 1/2 v cc 1/2 v cc
mb90210 series 64 (3) recommended resonator manufacturers (4) reset and hardware standby input standards single-chip mode mb90214/p214b/w214b : (v cc = +4.5 v to +5.5 v, v ss = 0.0 v, t a = C40 c to +105 c) MB90P214A/w214a : (v cc = +4.5 v to +5.5 v, v ss = 0.0 v, t a = C40 c to +85 c) external bus mode : (v cc = +4.5 v to +5.5 v, v ss = 0.0 v, t a = C40 c to +70 c) * : the machine cycle (t cyc ) at hardware standby input is set to 1/16 divided oscillation. parameter symbol pin name condition value unit remarks min. typ. max. reset input time t rstl rst 5 t cyc ns hardware standby input time t hstl hst 5 t cyc ns* x0 x1 c 1 c 2 *1: fujitsu acoustic resonator *2 *2 far *1 inquiry: fujitsu limited far part number (built-in capacitor type) frequency initial deviation of far frequency (t a = +25 c) temperature characteristics of far frequency (t a = C20 c to +60 c) load capacitance* 2 far-c4c f-1 6000- 02 16.00 0.5% 0.5% built-in far-c4c f-1 6000- 12 0.5% 0.5% sample application of piezoelectric resonator (far series) t rstl , t hstl rst hst 0.2 v cc 0.2 v cc
65 mb90210 series (5) power on supply specifications (power-on reset) single-chip mode mb90214/p214b/w214b : (v cc = +4.5 v to +5.5 v, v ss = 0.0 v, t a = C40 c to +105 c) MB90P214A/w214a : (v cc = +4.5 v to +5.5 v, v ss = 0.0 v, t a = C40 c to +85 c) external bus mode : (v cc = +4.5 v to +5.5 v, v ss = 0.0 v, t a = C40 c to +70 c) * : before the power rising, v cc must be less than +0.2 v. notes: the above specifications are for the power-on reset. always apply power-on reset using these specifications, regardless of whether or not the power-on reset is needed. there are some internal registers (such as stbyc) which are only initialized by the power-on reset. note: caution on switching power supply abrupt change of supply voltage may initiate power-on reset, even if the above requirements are not met. it is, therefore, recommended to power up gradually during the instantaneous change of power supply as shown in the figure below. parameter symbol pin name condition value unit remarks min. typ. max. power supply rising time t r v cc 30ms* power supply cut-off time t off v cc 1ms t r 0.2 v 0.2 v 4.5 v v cc t off 0.2 v power-on reset v ss main power supply voltage subpower supply voltage the rising edge should be 50 mv/ms or less. changing power supply
mb90210 series 66 (6) bus read timing (v cc = +4.5 to +5.5 , v ss = 0.0 v, t a = C40 c to +70 c) parameter symbol pin name condition value unit remarks min. max. valid address ? rd time t avr l a23 to a00 load condition: 80 pf t cyc /2 C 20 ns rd pulse width t rlrh rd t cyc C 25 ns rd ? valid data input t rldv d15 to d00 t cyc C 30 ns rd - ? data hold time t rhdx 0ns valid address ? valid data input t avdv 3 t cyc /2 C 40 ns rd - ? address valid time t rhax a23 to a00 t cyc /2 C 20 ns valid address ? clk - time t avc h a23 to a00 clk t cyc /2 C 25 ns rd ? clk time t rlcl rd , clk t cyc /2 C 25 ns t rlrh t rlcl t avch t avrl t rhax t rhdx t rldv t avdv 0.7 v cc 0.3 v cc 0.7 v cc 0.3 v cc clk 0.7 v cc 0.7 v cc 0.7 v cc 0.3 v cc 0.7 v cc 0.3 v cc 0.3 v cc 0.3 v cc rd a23 to a00 d15 to d00 read data
67 mb90210 series (7) bus write timing (v cc = +4.5 to +5.5 v, v ss = 0.0 v, t a = C40 c to +70 c) parameter symbol pin name condition value unit remarks min. max. valid address ? wr time t avwl a23 to a00 load condition: 80 pf t cyc /2 C 20 ns wr pulse width t wlwh wrl , wrh t cyc C 25 ns valid data output ? wr - time t dvwh d15 to d00 t cyc C 40 ns wr - ? data hold time t whdx t cyc /2 C 20 ns wr - ? address valid time t whax a23 to a00 t cyc /2 C 20 ns wr ? clk time t wlch wrl , wrh , clk t cyc /2 C 25 ns t wlwh t wlcl t whax clk wr (wrl, wrh) t whdx write data t dvwh t avwl un- defined 0.7 v cc 0.7 v cc 0.7 v cc 0.3 v cc 0.3 v cc 0.3 v cc 0.3 v cc a23 to a00 d15 to d00
mb90210 series 68 (8) ready signal input timing (v cc = +4.5 to +5.5 v, v ss = 0.0 v, t a = C40 c to +70 c) note: use the auto-ready function if the rdy setup time is insufficient. (9) hold timing (v cc = +4.5 to +5.5 v, v ss = 0.0 v, t a = C40 c to +70 c) note: it takes at least one cycle for hak to vary after hrq is fetched. parameter symbol pin name condition value unit remarks min. max. rdy setup time t ryhs rdy load condition: 80 pf 40 ns rdy hold time t ryhh 0ns parameter symbol pin name condition value unit remarks min. max. pin floating ? hak time t xhal hak load condition: 80 pf 30 t cyc ns hak - ? pin valid time t hahv t cyc 2t cyc ns t ryhs t ryhh t ryhs t ryhh clk 0.7 v cc 0.7 v cc 0.8 v cc 0.8 v cc 0.8 v cc 0.8 v cc 0.2 v cc a23 to a00 rd/wr (wrl, wrh) rdy no wait wait t xhal t hahv high impedance hrq hak each pin 0.8 v cc 0.2 v cc 0.3 v cc 0.7 v cc
69 mb90210 series (10) uart timing single-chip mode mb90214/p214b/w214b : (v cc = +4.5 v to +5.5 v, v ss = 0.0 v, t a = C40 c to +105 c) MB90P214A/w214a : (v cc = +4.5 v to +5.5 v, v ss = 0.0 v, t a = C40 c to +85 c) external bus mode : (v cc = +4.5 v to +5.5 v, v ss = 0.0 v, t a = C40 c to +70 c) notes: these ac characteristics assume the clk synchronous mode. t cyc is the machine cycle (unit: ns). parameter symbol pin name condition value unit remarks min. max. serial clock cycle time t scyc load condition: 80 pf 8 t cyc ns internal shift clock mode output pin sclk ? sout delay time t slov C80 80 ns valid sin ? sclk - t ivsh 100 ns sclk - ? valid sin hold time t shix 60 ns serial clock h pulse width t shsl 4 t cyc ns external shift clock mode output pin serial clock l pulse width t slsh 4 t cyc ns sclk ? sout delay time t slov 150 ns valid sin ? sclk - t ivsh 60 ns sclk - ? valid sin hold time t shix 60 ns
mb90210 series 70 t scyc t slov t ivsh t shix sck 0.3 v cc 0.7 v cc 0.2 v cc 0.8 v cc 0.7 v cc 0.3 v cc 0.8 v cc 0.2 v cc 0.7 v cc 0.3 v cc 0.8 v cc 0.2 v cc sid sod sck sid sod t slsh t slov t ivsh t shix t shsl 0.3 v cc 0.8 v cc 0.2 v cc 0.2 v cc 0.2 v cc 0.8 v cc 0.2 v cc internal shift clock mode external shift clock mode
71 mb90210 series (11) resource input timing single-chip mode mb90214/p214b/w214b : (v cc = +4.5 v to +5.5 v, v ss = 0.0 v, t a = C40 c to +105 c) MB90P214A/w214a : (v cc = +4.5 v to +5.5 v, v ss = 0.0 v, t a = C40 c to +85 c) external bus mode : (v cc = +4.5 v to +5.5 v, v ss = 0.0 v, t a = C40 c to +70 c) (12) resource output timing single-chip mode mb90214/p214b/w214b : (v cc = +4.5 v to +5.5 v, v ss = 0.0 v, t a = C40 c to +105 c) MB90P214A/w214a : (v cc = +4.5 v to +5.5 v, v ss = 0.0 v, t a = C40 c to +85 c) external bus mode : (v cc = +4.5 v to +5.5 v, v ss = 0.0 v, t a = C40 c to +70 c) parameter symbol pin name condition value unit remarks min. typ. max. input pulse width t tiwh t tiwl tin0 to tin3 load condition: 80 pf 4 t cyc ns external event count input mode 2 t cyc trigger input/ gate input mode tin4 to tin7 2 t cyc ns gate input mode pwc0 to pwc3 2 t cyc ns int0 to int3 3 t cyc ns at g 2 t cyc ns t wiwl wi 4 t cyc ns parameter symbol pin name condition value unit remarks min. max. clk - ? t out transition time t to tout0 to tout3 ppg pout0 to pout3 load condition: 80 pf 30ns t tiwh tin0 to tin7 pwc0 to pwc3 int0 to int3 wi 0.8 v cc 0.8 v cc 0.2 v cc 0.2 v cc t tiwl , t wiwl t to clk tout0 to tout3 ppg pout0 to pout3 0.7 v cc 0.7 v cc 0.3v cc
mb90210 series 72 5. a/d converter electrical characteristics single-chip mode mb90214/p214b/w214b: (av cc = v cc = +5.0 10%, av ss = v ss = 0.0 v, t a = C40 c to +105 c, +4.5 v avrh C avrl) single-chip mode mbp90214a/w214a: (av cc = v cc = +5.0 10%, av ss = v ss = 0.0 v, t a = C40 c to +85 c, +4.5 v avrh C avrl) external bus mode: (av cc = v cc = +5.0 10%, av ss = v ss = 0.0 v, t a = C40 c to +70 c, +4.5 v avrh C avrl) * : the current value applies to the cpu stop mode with the a/d converter inactive (v cc = av cc = avrh = +5.5 v). notes: (1) the smaller the | avrh C avrl |, the greater the error would become relatively. (2) use the output impedance of the external circuit for analog input under the following conditions: external circuit output impedance < approx. 10 k w (sampling period 3.75 m s, t cyc = 62.5 ns) (3) precision values are standard values applicable to sleep mode. (4) if v cc /av cc or v ss /av ss is caused by a noise to drop to below the analog input voltage, the analog input current is likely to increase. in such cases, a bypass capacitor or the like should be provided in the external circuit to suppress the noise. parameter symbol pin name condition value unit remarks min. typ. max. resolution n 10 bit total error C3.0 +3.0 lsb linearity error C2.0 +2.0 lsb differential linearity error 1.5 lsb zero transition voltage v ot an0 to an7 avrl C 1.5 avrl + 0.5 avrl + 2.5 lsb full-scale transition voltage v fst avrh C 3.5 avrh C 1.5 avrh + 0.5 lsb conversion time sampling period t conv t cyc = 62.5 ns 6.125 m s 98 machine cycles t samp 3.75 m s 60 machine cycles analog port input current i ain an0 to an7 0.1 m a analog input voltage v ain avrl avrh v analog reference voltage avrh avrl av cc v avrl av ss avrhv reference voltage supply current i r avrh 200500 m a i rh 5* m a interchannel disparity an0 to an7 4 lsb ? ? = . .
73 mb90210 series 6. a/d converter glossary resolution: analog changes that are identifiable with the a/d converter when the number of bits is 10, analog voltage can be divided into 2 10 = 1024. total error: difference between actual and logical values. this error is caused by a zero transition error, full-scale transition error, linearity error, differential linearity error, or by noise. linearity error: the deviation of the straight line connecting the zero transition point (00 0000 0000 ? 00 0000 0001) with the full-scale transition point (11 1111 1111 ? 11 1111 1110) from actual conversion characteristics differential linearity error: the deviation of input voltage needed to change the output code by 1 lsb from the theoretical value. equivalent circuit of analog input circuit note: the values shown here are reference values. analog input comparator c 1 c 0 r on2 r on1 r on1 : approx. 1.5 k w r on2 : approx. 1.5 k w c 0 : approx. 60 pf c 1 : approx. 4 pf external impedance digital output 11 1111 1111 11 1111 1110 11 1111 1101 n + 1 n n ?1 00 0000 0010 00 0000 0001 00 0000 0000 1lsb v fst ?v 0t 1022 = av rh ?av rl 1022 = linearity error 1lsb theoretical value v nt ?(n 1lsb + v 0t ) = 1lsb n = 0 to 1022 v nt (n = 0) = v 0t v nt (n = 1022) = v fst differential linearity error v nt ?v (n ?1) t = 1lsb ?1 n = 1 to 1022 total error v nt ?{ ( n + 0.5 ) 1lsb theoretical value } = 1lsb theoretical value n = 0 to 1022 v fst v 0t v (n?)t theoretical value actual conversion value total error linerity error v 1t v 2t v (n+1)t v nt avrh (v) avrl n 1lsb + v 0t theoretical value v nt
mb90210 series 74 n example characteristics (1) power supply current note: these are not assured value of characteristics but example characteristics. (2) output voltage note: these are not assured value of characteristics but example characteristics. i cc vs. t a example characteristics ?0 0 50 100 150 t a ( c) 100 90 80 70 60 50 40 i cc (ma) f c = 16 mhz external clock input v cc = 5.5 v MB90P214A mb90214 i cch vs. t a example characteristics ?0 0 50 100 150 t a ( c) 40 30 20 10 0 ?0 i cch ( m a) v cc = 5.5 v v oh vs. i oh example characteristics ?5 ?0 ? 0 5 i oh (ma) 5.5 5.0 4.5 4.0 3.5 3.0 v oh (v) t a = +25 c v cc = 5.0 v v ol vs. i ol example characteristics ? 0 5 10 15 i ol (ma) 2.0 1.5 1.0 0.5 0.0 ?.5 v ol (v) 20 25 t a = +25 c v cc = 5.0 v
75 mb90210 series (3) pull-up/pull-down resistor note: these are not assured value of characteristics but example characteristics. (4) analog filter note: these are not assured value of characteristics but example characteristics. pull-down resistor example characteristics ?0 0 50 100 150 t a ( c) 100 90 80 70 60 50 40 30 20 r pul d (k w ) v cc = 4.5 v v cc = 5.0 v v cc = 5.5 v pull-up resistor example characteristics ?0 0 50 100 150 t a ( c) 100 90 80 70 60 50 40 30 20 r pul u (k w ) v cc = 4.5 v v cc = 5.0 v v cc = 5.5 v pull-up resistor example characteristics ?0 0 50 100 150 t a ( c) 500 400 300 200 100 r pul u (k w ) v cc = 5.5 v pull-down resistor example characteristics ?0 0 50 100 150 t a ( c) 500 400 300 200 100 r pul d (k w ) v cc = 5.5 v analog filter example characteristics 4.0 4.5 5.0 5.5 6.0 v cc (v) 80 70 60 50 40 30 20 10 input pulse width (ns) filtering enable t a = +25 c
mb90210 series 76 n instructions (421 instructions) table 1 description of items in instruction list item description mnemonic english upper case and symbol: described directly in assembler code. english lower case: converted in assembler code. number of letters after english lower case: describes bit width in code. # describes number of bytes. ~ describes number of cycles. for other letters in other items, refer to table 4. b describes correction value for calculating number of actual states. number of actual states is calculated by adding value in the ~section. operation describes operation of instructions. lh describes a special operation to 15 bits to 08 bits of the accumulator. z : transfer 0. x : sign-extend and transfer. C : no transmission ah describes a special operation to the upper 16-bit of the accumulator. * : transmit from al to ah. C : no transfer. z : transfer 00 h to ah. x : sign-extend al and transfer 00 h or ff h to ah. i describes status of i (interrupt enable), s (stack), t (sticky bit), n (negative), z (zero), v (overflow), and c (carry) flags. * : changes after execution of instruction. C : no changes. s : set after execution of instruction. r : reset after execution of instruction. s t n z v c rmw describes whether or not the instruction is a read-modify-write type (a data is read out from memory etc. in single cycle, and the result is written into memory etc.). * : read-modify-write instruction C : not read-modify-write instruction note: not used to addresses having different functions for reading and writing operations.
77 mb90210 series table 2 description of symbols in instruction table item description a 32-bit accumlator the bit length is dependent on the instructions to be used. byte : lower 8-bit of al word :16-bit of al long : al: 32-bit of ah ah upper 16-bit of a al lower 16-bit of a sp stack pointer (usp or ssp) pc program counter spcu stack pointer upper limited register spcl stack pointer lower limited register pcb program bank register dtb data bank register adb additional data bank register ssb system stack bank register usb user stack bank register spb current stack bank register (ssb or usb) dpr direct page register brg1 dtb, adb, ssb, usb, dpr, pcb brg2 dtb, adb, ssb, usb, dpr ri r0, r1, r2, r3, r4, r5, r6, r7 rwi rw0, rw1, rw2, rw3, rw4, rw5, rw6, rw7 rwj rw0, rw1, rw2, rw3 rli rl0, rl1, rl2, rl3 dir addr16 addr24 ad24 0 to 15 ad24 16 to 23 specify shortened direct address. specify direct address. specify physical direct address. bit0 to bit15 of addr24 bit16 to bit 23 of addr24 io i/o area (000000 h to 0000ff h ) #imm4 #imm8 #imm16 #imm32 ext (imm8) 4-bit immediate data 8-bit immediate data 16-bit immediate data 32-bit immediate data 16-bit data calculated by sign-extending an 8-bit immediate data disp8 disp16 8-bit displacement 16-bit displacement bp bit offset value vct4 vct8 vector number (0 to 15) vector number (0 to 255) ( )b bit address rel ear eam specify pc relative branch. specify effective address (code 00 to 07). specify effective address (code 08 to 1f). rlst register allocation
mb90210 series 78 table 3 effective address field note: number of bytes for address extension corresponds to + in the # (number of bytes) part in the instruction table. code symbol address type number of bytes in address extension block* 00 01 02 03 04 05 06 07 r0 r1 r2 r3 r4 r5 r6 r7 rw0 rw1 rw2 rw3 rw4 rw5 rw6 rw7 rl0 (rl0) rl1 (rl1) rl2 (rl2) rl3 (rl3) register direct "ea" corresponds to byte, word, and long word from left respectively. 08 09 0a 0b @rw0 @rw1 @rw2 @rw3 register indirect 0 0c 0d 0e 0f @rw0 + @rw1 + @rw2 + @rw3 + register indirect with post increment 0 10 11 12 13 14 15 16 17 @rw0 + disp8 @rw1 + disp8 @rw2 + disp8 @rw3 + disp8 @rw4 + disp8 @rw5 + disp8 @rw6 + disp8 @rw7 + disp8 register indirect with 8-bit displacement 1 18 19 1a 1b @rw0 + disp16 @rw1 + disp16 @rw2 + disp16 @rw3 + disp16 register indirect with 16-bit displacement 2 1c 1d 1e 1f @rw0 + rw7 @rw1 + rw7 @pc + disp16 addr16 register indirect with index register indirect with index pc indirect with 16-bit displacement direct address 0 0 2 2
79 mb90210 series table 4 number of execution cycles in addressing modes note: (a) is used for ~ (number of cycles) and b (correction value) in instruction table. table 5 correction value for number of cycles for calculating actual number of cycles notes: (b), (c), (d) is used for ~ (number of cycles) and b (correction value) in instruction table. code operand (a)* number of execution cycles for addressing modes 00 to 07 ri rwi rli listed in instruction table 08 to 0b @rwj 1 0c to 0f @rwj + 4 10 to 17 @rwi + disp8 1 18 to 1b @rwj + disp16 1 1c 1d 1e 1f @rw0 + rw7 @rw1 + rw7 @pc + disp16 addr16 2 2 2 1 operand (b)* (c)* (d)* byte word long internal register +0 +0 +0 internal ram even address internal ram odd address +0 +0 +0 +1 +0 +2 other than internal ram even address other than internal ram odd address +1 +1 +1 +3 +2 +6 external data bus 8-bit +1 +3 +6
mb90210 series 80 table 6 transmission instruction (byte) [50 instructions] note: for (a) and (b), refer to table 4 number of execution cycles in addressing modes and table 5 correction values for number of cycles for calculating actual number of cycles. mnemonic # ~ b operation lh ah istnzvcrmw mov a, dir mov a, addr16 mov a, ri mov a, ear mov a, eam mov a, io mov a, #imm8 mov a, @a mov a, @rli + disp8 mov a, @sp + disp8 movp a, addr24 movp a, @a movn a, #imm4 movx a, dir movx a, addr16 movx a, ri movx a, ear movx a, eam movx a, io movx a, #imm8 movx a, @a movx a, @rwi + disp8 movx a, @rli + disp8 movx a, @sp + disp8 movpx a, addr24 movpx a, @a mov dir, a mov addr16, a mov ri, a mov ear, a mov eam, a mov io, a mov @rli + disp8, a mov @sp + disp8, a movp addr24, a mov ri, ear mov ri, eam movp @a, ri mov ear, ri mov eam, ri mov ri, #imm8 mov io, #imm8 mov dir, #imm8 mov ear, #imm8 mov eam, #imm8 mov @al, ah xch a, ear xch a, eam xch ri, ear xch ri, eam 2 3 1 2 2 + 2 2 2 3 3 5 2 1 2 3 2 2 2 + 2 2 2 2 3 3 5 2 2 3 1 2 2 + 2 3 3 5 2 2 + 2 2 2 + 2 3 3 3 3 + 2 2 2 + 2 2 + 2 2 1 1 2 + (a) 2 2 2 6 3 3 2 1 2 2 1 1 2 + (a) 2 2 2 3 6 3 3 2 2 2 1 2 2 + (a) 2 6 3 3 2 3 + (a) 3 3 3 + (a) 2 3 3 2 2 + (a) 2 3 3 + (a) 4 5 + (a) (b) (b) 0 0 (b) (b) 0 (b) (b) (b) (b) (b) 0 (b) (b) 0 0 (b) (b) 0 (b) (b) (b) (b) (b) (b) (b) (b) 0 0 (b) (b) (b) (b) (b) 0 (b) (b) 0 (b) 0 (b) (b) 0 (b) (b) 0 2 (b) 0 2 (b) byte (a) ? (dir) byte (a) ? (addr16) byte (a) ? (ri) byte (a) ? (ear) byte (a) ? (eam) byte (a) ? (io) byte (a) ? imm8 byte (a) ? ((a)) byte (a) ? ((rli) + disp8) byte (a) ? ((sp) + disp8) byte (a) ? (addr24) byte (a) ? ((a)) byte (a) ? imm4 byte (a) ? (dir) byte (a) ? (addr16) byte (a) ? (ri) byte (a) ? (ear) byte (a) ? (eam) byte (a) ? (io) byte (a) ? imm8 byte (a) ? ((a)) byte (a) ? ((rwi) + disp8) byte (a) ? ((rli) + disp8) byte (a) ? ((sp) + disp8) byte (a) ? (addr24) byte (a) ? ((a)) byte (dir) ? (a) byte (addr16) ? (a) byte (ri) ? (a) byte (ear) ? (a) byte (eam) ? (a) byte (io) ? (a) byte ((rli) + disp8) ? (a) byte ((sp) + disp8) ? (a) byte (addr24) ? (a) byte (ri) ? (ear) byte (ri) ? (eam) byte ((a)) ? (ri) byte (ear) ? (ri) byte (eam) ? (ri) byte (ri) ? imm8 byte (io) ? imm8 byte (dir) ? imm8 byte (ear) ? imm8 byte (eam) ? imm8 byte ((a)) ? (ah) byte (a) ? (ear) byte (a) ? (eam) byte (ri) ? (ear) byte (ri) ? (eam) z z z z z z z z z z z z z x x x x x x x x x x x x x C C C C C C C C C C C C C C C C C C C C z z C C * * * * * * * C * * * C * * * * * * * * C * * * * C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C * * * * * * * * * * * * r * * * * * * * * * * * * * * * * * * * * * * * * * * * * C C * C * C C C C * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * C C * C * C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C
81 mb90210 series table 7 transmission instruction (word) [40 instructions] note: for (a) and (c), refer to table 4 number of execution cycles in addressing modes and table 5 correction values for number of cycles for calculating actual number of cycles. mnemonic # ~ b operation lh ah istnzvcrmw movw a, dir movw a, addr16 movw a, sp movw a, rwi movw a, ear movw a, eam movw a, io movw a, @a movw a, #imm16 movw a, @rwi + disp8 movw a, @rli + disp8 movw a, @sp + disp8 movpw a, addr24 movpw a, @a movw dir, a movw addr16, a movw sp, #imm16 movw sp, a movw rwi, a movw ear, a movw eam, a movw io, a movw @rwi + disp8, a movw @rli + disp8, a movw @sp + disp8, a movpw addr24, a movpw @a, rwi movw rwi, ear movw rwi, eam movw ear, rwi movw eam, rwi movw rwi, #imm16 movw io, #imm16 movw ear, #imm16 movw eam, #imm16 movw @al, ah xchw a, ear xchw a, eam xchw rwi, ear xchw rwi, eam 2 3 1 1 2 2 + 2 2 3 2 3 3 5 2 2 3 4 1 1 2 2 + 2 2 3 3 5 2 2 2 + 2 2 + 3 4 4 4 + 2 2 2 + 2 2 + 2 2 2 1 1 2 + (a) 2 2 2 3 6 3 3 2 2 2 2 2 1 2 2 + (a) 2 3 6 3 3 3 2 3 + (a) 3 3 + (a) 2 3 2 2 + (a) 2 3 3 + (a) 4 5 + (a) (c) (c) 0 0 0 (c) (c) (c) 0 (c) (c) (c) (c) (c) (c) (c) 0 0 0 0 (c) (c) (c) (c) (c) (c) (c) 0 (c) 0 (c) 0 (c) 0 (c) (c) 0 2 (c) 0 2 (c) word (a) ? (dir) word (a) ? (addr16) word (a) ? (sp) word (a) ? (rwi) word (a) ? (ear) word (a) ? (eam) word (a) ? (io) word (a) ? ((a)) word (a) ? imm16 word (a) ? ((rwi) +disp8) word (a) ? ((rli) +disp8) word (a) ? ((sp) + disp8) word (a) ? (addr24) word (a) ? ((a)) word (dir) ? (a) word (addr16) ? (a) word (sp) ? imm16 word (sp) ? (a) word (rwi) ? (a) word (ear) ? (a) word (eam) ? (a) word (io) ? (a) word ((rwi) +disp8) ? (a) word ((rli) +disp8) ? (a) word ((sp) + disp8) ? (a) word (addr24) ? (a) word ((a)) ? (rwi) word (rwi) ? (ear) word (rwi) ? (eam) word (ear) ? (rwi) word (eam) ? (rwi) word (rwi) ? imm16 word (io) ? imm16 word (ear) ? imm16 word (eam) ? imm16 word ((a)) ? (ah) word (a) ? (ear) word (a) ? (eam) word (rwi) ? (ear) word (rwi) ? (eam) C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C * * * * * * * C * * * * * C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * C * C * C C C C * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * C * C * C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C
mb90210 series 82 table 8 transmission instruction (long) [11 instructions] note: for (a) and (c), refer to table 4 number of execution cycles in addressing modes and table 5 correction values for number of cycles for calculating actual number of cycles. mnemonic # ~ b operation lh ah istnzvcrmw movl a, ear 2 2 0 long (a) ? (ear) CCCCC* *CC C movl a, eam 2 + 3 + (a) (d) long (a) ? (eam) CCCCC* *CC C movl a, #imm32 5 3 0 long (a) ? imm32 CCCCC* *CC C movl a, @sp + disp8 3 4 (d) long (a) ? ((sp) + disp8) CCCCC* *CC C movpl a, addr24 5 4 (d) long (a) ? (addr24) CCCCC* *CC C movpl a, @a 2 3 (d) long (a) ? ((a)) CCCCC* *CC C movpl @a, rli 2 5 (d) long ((a)) ? (rli) CCCCC* *CC C movl @sp + disp8, a 3 4 (d) long ((sp) + disp8) ? (a) CCCCC* *CC C movpl addr24, a 5 4 (d) long (addr24) ? (a) CCCCC* *CC C movl ear, a 2 2 0 long (ear) ? (a) CCCCC* *CC C movl eam, a 2 + 3 + (a) (d) long (eam) ? (a) CCCCC* *CC C
83 mb90210 series table 9 add/subtract (byte, word, long) [42 instructions] note: for (a) to (d), refer to table 4 number of execution cycles in addressing modes and table 5 correction values for number of cycles for calculating actual number of cycles. mnemonic # ~ b operation lh ah istnzvcrmw add a,#imm8 add a, dir add a, ear add a, eam add ear, a add eam, a addc a addc a, ear addc a, eam adddc a sub a, #imm8 sub a, dir sub a, ear sub a, eam sub ear, a sub eam, a subc a subc a, ear subc a, eam subdc a 2 2 2 2 + 2 2 + 1 2 2 + 1 2 2 2 2 + 2 2 + 1 2 2 + 1 2 3 2 3 + (a) 2 3 + (a) 2 2 3 + (a) 3 2 3 2 3 + (a) 2 3 + (a) 2 2 3 + (a) 3 0 (b) 0 (b) 0 2 (b) 0 0 (b) 0 0 (b) 0 (b) 0 2 (b) 0 0 (b) 0 byte (a) ? (a) +imm8 byte (a) ? (a) +(dir) byte (a) ? (a) +(ear) byte (a) ? (a) +(eam) byte (ear) ? (ear) + (a) byte (eam) ? (eam) + (a) byte (a) ? (ah) + (al) + (c) byte (a) ? (a) + (ear) + (c) byte (a) ? (a) + (eam) + (c) byte (a) ? (ah) + (al) + (c) (decimal) byte (a) ? (a) C imm8 byte (a) ? (a) C (dir) byte (a) ? (a) C (ear) byte (a) ? (a) C (eam) byte (ear) ? (ear) C (a) byte (eam) ? (eam) C (a) byte (a) ? (ah) C (al) C (c) byte (a) ? (a) C (ear) C (c) byte (a) ? (a) C (eam) C (c) byte (a) ? (ah) C (al) C (c) (decimal) z z z z C z z z z z z z z z C C z z z z C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * C C C C * * C C C C C C C C * * C C C C addw a addw a, ear addw a, eam addw a, #imm16 addw ear, a addw eam, a addcw a, ear addcw a, eam subw a subw a, ear subw a, eam subw a, #imm16 subw ear, a subw eam, a subcw a, ear subcw a, eam 1 2 2 + 3 2 2 + 2 2 + 1 2 2 + 3 2 2 + 2 2 + 2 2 3 + (a) 2 2 3 + (a) 2 3 + (a) 2 2 3 + (a) 2 2 3 + (a) 2 3 + (a) 0 0 (c) 0 0 2 (c) 0 (c) 0 0 (c) 0 0 2 (c) 0 (c) word (a) ? (ah) + (al) word (a) ? (a) + (ear) word (a) ? (a) + (eam) word (a) ? (a) + imm16 word (ear) C (ear) + (a) word (eam) C (eam) + (a) word (a) ? (a) + (ear) + (c) word (a) ? (a) + (eam) + (c) word (a) ? (ah) C (al) word (a) ? (a) C (ear) word (a) ? (a) C (eam) word (a) ? (a) C imm16 word (ear) ? (ear) C (a) word (eam) ? (eam) C (a) word (a) ? (a) C (ear) C (c) word (a) ? (a) C (eam) C (c) C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * C C C C * * C C C C C C * * C C addl a, ear addl a, eam addl a, #imm32 subl a, ear subl a, eam subl a, #imm32 2 2 + 5 2 2 + 5 5 6 + (a) 4 5 6 + (a) 4 0 (d) 0 0 (d) 0 long (a) ? (a) + (ear) long (a) ? (a) + (eam) long (a) ? (a) + imm32 long (a) ? (a) C (ear) long (a) ? (a) C (eam) long (a) ? (a) C imm32 C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C * * * * * * * * * * * * * * * * * * * * * * * * C C C C C C
mb90210 series 84 table 10 increment/decrement (byte, word, long) [12 instructions] note: for (a) to (d), refer to table 4 number of execution cycles in addressing modes and table 5 correction values for number of cycles for calculating actual number of cycles. table 11 compare (byte, word, long) [11 instructions] note: for (a) to (d), refer to table 4 number of execution cycles in addressing modes and table 5 correction values for number of cycles for calculating actual number of cycles. mnemonic # ~ b operation lh ah istnzvcrmw inc ear inc eam dec ear dec eam 2 2 + 2 2 + 2 3 + (a) 2 3 + (a) 0 2 (b) 0 2 (b) byte (ear) ? (ear) +1 byte (eam) ? (eam) +1 byte (ear) ? (ear) C1 byte (eam) ? (eam) C1 C C C C C C C C C C C C C C C C C C C C * * * * * * * * * * * * C C C C * * * * incw ear incw eam decw ear decw eam 2 2 + 2 2 + 2 3 + (a) 2 3 + (a) 0 2 (c) 0 2 (c) word (ear) ? (ear) +1 word (eam) ? (eam) +1 word (ear) ? (ear) C1 word (eam) ? (eam) C1 C C C C C C C C C C C C C C C C C C C C * * * * * * * * * * * * C C C C * * * * incl ear incl eam decl ear decl eam 2 2 + 2 2 + 4 5 + (a) 4 5 + (a) 0 2 (d) 0 2 (d) long (ear) ? (ear) +1 long (eam) ? (eam) +1 long (ear) ? (ear) C1 long (eam) ? (eam) C1 C C C C C C C C C C C C C C C C C C C C * * * * * * * * * * * * C C C C C * * * mnemonic # ~ b operation lh ah istnzvcrmw cmp a cmp a, ear cmp a, eam cmp a, #imm8 1 2 2 + 2 1 2 3 + (a) 2 0 0 (b) 0 byte (ah) C (al) byte (a) C (ear) byte (a) C (eam) byte (a) C imm8 C C C C C C C C C C C C C C C C C C C C * * * * * * * * * * * * * * * * C C C C cmpw a cmpw a, ear cmpw a, eam cmpw a, #imm16 1 2 2 + 3 1 2 3 + (a) 2 0 0 (c) 0 word (ah) C (al) word (a) C (ear) word (a) C (eam) word (a) C imm16 C C C C C C C C C C C C C C C C C C C C * * * * * * * * * * * * * * * * C C C C cmpl a, ear cmpl a, eam cmpl a, #imm32 2 2 + 5 6 7 + (a) 3 0 (d) 0 word (a) C (ear) word (a) C (eam) word (a) C imm32 C C C C C C C C C C C C C C C * * * * * * * * * * * * C C C
85 mb90210 series table 12 unsigned multiply/division (word, long) [11 instructions] note: for (b) and (c), refer to table 5 correction values for number of cycles for calculating actual number of cycles. *1: set to 3 when the division-by-0, 6 for an overflow, and 14 for normal operation. *2: set to 3 when the division-by-0, 6 for an overflow, and 13 for normal operation. *3: set to 5 + (a) when the division-by-0, 7 + (a) for an overflow, and 17 + (a) for normal operation. *4: set to 3 when the division-by-0, 5 for an overflow, and 21 for normal operation. *5: set to 4 + (a) when the division-by-0, 7 + (a) for an overflow, and 25 + (a) for normal operation. *6: when the division-by-0, (b) for an overflow, and 2 (b) for normal operation. *7: when the division-by-0, (c) for an overflow, and 2 (c) for normal operation. *8: set to 3 when byte (ah) is zero, 7 when byte (ah) is not zero. *9: set to 3 when byte (ear) is zero, 7 when byte (ear) is not zero. *10:set to 4 + (a) when byte (eam) is zero, 8 + (a) when byte (eam) is not zero. *11:set to 3 when word (ah) is zero, 11 when word (ah) is not zero. *12:set to 4 when word (ear) is zero, 11 when word (ear) is not zero. *13:set to 4 + (a) when word (eam) is zero, 12 + (a) when word (eam) is not zero. mnemonic # ~ b operation lh ah istnzvcrmw divu a divu a, ear divu a, eam divuw a, ear divuw a, eam mulu a mulu a, ear mulu a, eam muluw a muluw a, ear muluw a, eam 1 2 2 + 2 2+ 1 2 2 + 1 2 2 + *1 *2 *3 *4 *5 *8 *9 *10 *11 *12 *13 0 0 *6 0 *7 0 0 (b) 0 0 (c) word (ah) /byte (al) quotient ? byte (al) remainder ? byte (ah) word (a)/byte (ear) quotient ? byte (a) remainder ? byte (ear) word (a)/byte (eam) quotient ? byte (a) remainder ? byte (eam) long (a)/word (ear) quotient ? word (a) remainder ? word (ear) long (a)/word (eam) quotient ? word (a) remainder ? word (eam) byte (ah) byte (al) ? word (a) byte (a) byte (ear) ? word (a) byte (a) byte (eam) ? word (a) word (ah) word (al) ? long (a) word (a) word (ear) ? long (a) word (a) word (eam) ? long (a) C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C * * * * * C C C C C C * * * * * C C C C C C C C C C C C C C C C C
mb90210 series 86 table 13 signed multiplication/division (word, long) [11 instructions] for (b) and (c), refer to table 5 correction values for number of cycles for calculating actual number of cycles. *1: set to 3 for divide-by-0, 8 or 18 for an overflow, and 18 for normal operation. *2: set to 3 for divide-by-0, 10 or 21 for an overflow, and 22 for normal operation. *3: set to 4 + (a) for divide-by-0, 11 + (a) or 22 + (a) for an overflow, and 23 + (a) for normal operation. *4: positive divided: set to 4 for divide-by-0, 10 or 29 for an overflow, and 30 for normal operation. negative divided: set to 4 for divide-by-0, 11 or 30 for an overflow, and 31 for normal operation. *5: positive divided: set to 4 + (a) for divide-by-0, 11 + (a) or 30 + (a) for an overflow, and 31 + (a) for normal operation. negative divided: set to 4 + (a) for divide-by-0, 12 + (a) or 31 + (a) for an overflow, and 32 + (a) for normal operation. *6: set to (b) when the division-by-0 or an overflow, and 2 (b) for normal operation. *7: set to (c) when the division-by-0 or an overflow, and 2 (c) for normal operation. *8: set to 3 when byte (ah) is zero, 12 when the result is positive, and 13 when the result is negative. *9: set to 3 when byte (ear) is zero, 12 when the result is positive, and 13 when the result is negative. *10:set to 4 + (a) when byte (eam) is zero, 13 + (a) when the result is positive, and 14 + (a) when the result is negative. *11:set to 3 when word (ah) is zero, 12 when the result is positive, and 13 when the result is negative. *12:set to 3 when word (ear) is zero, 16 when the result is positive, and 19 when the result is negative. *13:set to 4 + (a) when word (eam) is zero, 17 + (a) when the result is positive, and 20 + (a) when the result is negative. note: when overflow occurs during div or divw instruction execution, the number of execution cycles takes two values because of detection before and after an operation. when overflow occurs during div or divw instruction execution, the contents of al are destroyed. mnemonic # ~ b operation lh ah istnzvcrmw div a 2 *1 0word (ah)/byte (al) zCCCCCC* * C quotient ? byte (al) remainder ? byte (ah) div a, ear 2 *2 0word (a)/byte (ear) zCCCCCC* * C quotient ? byte (a) remainder ? byte (ear) div a, eam 2 +*3*6word (a)/byte (eam) zCCCCCC* * C quotient ? byte (a) remainder ? byte (eam) divw a, ear 2 *4 0 long (a)/word (ear) C C C CCCC* * C quotient ? word (a) remainder ? word (ear) divw a, eam 2 + *5 *7 long (a)/word (eam) C C C CCCC* * C quotient ? word (a) remainder ? word (eam) mul a 2 *8 0 byte (ah) byte (al) ? word (a)CCCCCCCCC C mul a, ear 2 *9 0 byte (a) byte (ear) ? word (a) CCCCCCCCC C mul a, eam 2 + *10 (b) byte (a) byte (eam) ? word (a) CCCCCCCCC C mulw a 2 *11 0 word (ah) word (al) ? long (a) CCCCCCCCC C mulw a, ear 2 *12 0 word (a) word (ear) ? long (a) CCCCCCCCC C mulw a, eam 2 + *13 (b) word (a) word (eam) ? long (a) CCCCCCCCC C
87 mb90210 series table 14 logic 1 (byte, word) [39 instructions ] note: for (a) to (c), refer to table 4 number of execution cycles in addressing modes and table 5 correction values for number of cycles for calculating actual number of cycles. mnemonic # ~ b operation lh ah istnzvcrmw and a, #imm8 and a, ear and a, eam and ear, a and eam, a or a, #imm8 or a, ear or a, eam or ear, a or eam, a xor a, #imm8 xor a, ear xor a, eam xor ear, a xor eam, a not a not ear not eam 2 2 2 + 2 2 + 2 2 2 + 2 2 + 2 2 2 + 2 2 + 1 2 2 + 2 2 3 + (a) 3 3 + (a) 2 2 3 + (a) 3 3 + (a) 2 2 3 + (a) 3 3 + (a) 2 2 3 + (a) 0 0 (b) 0 2 (b) 0 0 (b) 0 2 (b) 0 0 (b) 0 2 (b) 0 0 2 (b) byte (a) ? (a) and imm8 byte (a) ? (a) and (ear) byte (a) ? (a) and (eam) byte (ear) ? (ear) and (a) byte (eam) ? (eam) and (a) byte (a) ? (a) or imm8 byte (a) ? (a) or (ear) byte (a) ? (a) or (eam) byte (ear) ? (ear) or (a) byte (eam) ? (eam) or (a) byte (a) ? (a) xor imm8 byte (a) ? (a) xor (ear) byte (a) ? (a) xor (eam) byte (ear) ? (ear) xor (a) byte (eam) ? (eam) xor (a) byte (a) ? not (a) byte (ear) ? not (ear) byte (eam) ? not (eam) C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * r r r r r r r r r r r r r r r r r r C C C C C C C C C C C C C C C C C C C C C * * C C C * * C C C * * C * * andw a andw a, #imm16 andw a, ear andw a, eam andw ear, a andw eam, a orw a orw a, #imm16 orw a, ear orw a, eam orw ear, a orw eam, a xorw a xorw a, #imm16 xorw a, ear xorw a, eam xorw ear, a xorw eam, a notw a notw ear notw eam 1 3 2 2 + 2 2 + 1 3 2 2 + 2 2 + 1 3 2 2 + 2 2 + 1 2 2 + 2 2 2 3 + (a) 3 3 + (a) 2 2 2 3 + (a) 3 3 + (a) 2 2 2 3 + (a) 3 3 + (a) 2 3 3 + (a) 0 0 0 (c) 0 2 (c) 0 0 0 (c) 0 2 (c) 0 0 0 (c) 0 2 (c) 0 0 2 (c) word (a) ? (ah) and (a) word (a) ? (a) and imm16 word (a) ? (a) and (ear) word (a) ? (a) and (eam) word (ear) ? (ear) and (a) word (eam) ? (eam) and (a) word (a) ? (ah) or (a) word (a) ? (a) or imm16 word (a) ? (a) or (ear) word (a) ? (a) or (eam) word (ear) ? (ear) or (a) word (eam) ? (eam) or (a) word (a) ? (ah) xor (a) word (a) ? (a) xor imm16 word (a) ? (a) xor (ear) word (a) ? (a) xor (eam) word (ear) ? (ear) xor (a) word (eam) ? (eam) xor (a) word (a) ? not (a) word (ear) ? not (ear) word (eam) ? not (eam) C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * r r r r r r r r r r r r r r r r r r r r r C C C C C C C C C C C C C C C C C C C C C C C C C * * C C C C * * C C C C * * C * *
mb90210 series 88 table 15 logic 2 (long) [6 instructions] note: for (a) and (d), refer to table 4 number of execution cycles in addressing modes and table 5 correction values for number of cycles for calculating actual number of cycles. table 16 sign reverse (byte, word) [6 instructions] note: for (a) and (d), refer to table 4 number of execution cycles in addressing modes and table 5 correction values for number of cycles for calculating actual number of cycles. table 17 absolute values (byte, word, long) [3 instructions] table 18 normalize instruction (long) [1 instruction] * : set to 5 when the accumulator is all 0, otherwise set to 5 + (r0). mnemonic # ~ b operation lh ah istnzvcrmw andl a, ear andl a, eam orl a, ear orl a, eam xorl a, ear xorl a, eam 2 2 + 2 2 + 2 2 + 5 6 + (a) 5 6 + (a) 5 6 + (a) 0 (d) 0 (d) 0 (d) long (a) ? (a) and (ear) long (a) ? (a) and (eam) long (a) ? (a) or (ear) long (a) ? (a) or (eam) long (a) ? (a) xor (ear) long (a) ? (a) xor (eam) C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C * * * * * * * * * * * * r r r r r r C C C C C C C C C C C C mnemonic # ~ rg b operation lh ah istnzvc rmw neg a neg ear neg eam 1 2 2 + 2 3 5 + (a) 0 2 0 0 0 2 (b) byte (a) ? 0 C (a) byte (ear) ? 0 C (ear) byte (eam) ? 0 C (eam) x C C C C C C C C C C C C C C * * * * * * * * * * * * C C * negw a negw ear negw eam 1 2 2 + 2 3 5 + (a) 0 2 0 0 0 2 (c) word (a) ? 0 C (a) word (ear) ? 0 C (ear) word (eam) ? 0 C (eam) C C C C C C C C C C C C C C C * * * * * * * * * * * * C C * mnemonic # ~ b operation lh ah istnzvcrmw abs a absw a absl a 2 2 2 2 2 4 0 0 0 byte (a) ? absolute value (a) word (a) ? absolute value (a) long (a) ? absolute value (a) z C C C C C C C C C C C C C C * * * * * * * * * C C C C C C mnemonic # ~ rg b operation lh ah istnzvc rmw nrml a, r0 2 *1 1 0 long (a) ? shift to where 1 is originally located byte (r0) ? number of shifts in the operation CCCCCC*CC C
89 mb90210 series table 19 shift type instruction (byte, word, long) [27 instructions] note: for (a) and (b), refer to table 4 number of execution cycles in addressing modes and table 5 correction values for number of cycles for calculating actual number of cycles. *1: set to 3 when r0 is 0, otherwise 3 + (r0). *2: set to 3 when r0 is 0, otherwise 4 + (r0). *3: set to 3 when imm8 is 0, otherwise 3 + imm8. *4: set to 3 when imm8 is 0, otherwise 4 + imm8. mnemonic # ~ b operation lh ah istnzvc rmw rorc a rolc a rorc ear rorc eam rolc ear rolc eam asr a, r0 lsr a, r0 lsl a, r0 asr a, #imm8 lsr a, #imm8 lsl a, #imm8 2 2 2 2 + 2 2 + 2 2 2 3 3 3 2 2 2 3 + (a) 2 3 + (a) *1 *1 *1 *3 *3 *3 0 0 0 2 (b) 0 2 (b) 0 0 0 0 0 0 byte (a) ? with right-rotate carry byte (a) ? with left-rotate carry byte (ear) ? with right-rotate carry byte (eam) ? with right-rotate carry byte (ear) ? with left-rotate carry byte (eam) ? with left-rotate carry byte (a) ? arithmetic right barrel shift (a, r0) byte (a) ? logical right barrel shift (a, r0) byte (a) ? logical left barrel shift (a, r0) byte (a) ? arithmetic right barrel shift (a, imm8) byte (a) ? logical right barrel shift (a, imm8) byte (a) ? logical left barrel shift (a, imm8) C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C * * C * * C * * * * * * * * * * * * * * * * * * * * * * * * C C C C C C C C C C C C * * * * * * * * * * * * C C * * * * C C C C C C asrw a lsrw a/shrw a lslw a/shlw a asrw a, r0 lsrw a, r0 lslw a, r0 asrw a, #imm8 lsrw a, #imm8 lslw a, #imm8 1 1 1 2 2 2 3 3 3 2 2 2 *1 *1 *1 *3 *3 *3 0 0 0 0 0 0 0 0 0 word (a) ? arithmetic right shift (a, 1 bit) word (a) ? logical right shift (a, 1 bit) word (a) ? logical left shift (a, 1 bit) word (a) ? arithmetic right barrel shift (a, r0) word (a) ? logical right barrel shift (a, r0) word (a) ? logical left barrel shift (a, r0) word (a) ? arithmetic right barrel shift (a, imm8) word (a) ? logical right barrel shift (a, imm8) word (a) ? logical left barrel shift (a, imm8) C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C * * C * * C * * C * r * * * * * * * * * * * * * * * * C C C C C C C C C * * * * * * * * * C C C C C C C C C asrl a, r0 lsrl a, r0 lsll a, r0 asrl a, #imm8 lsrl a, #imm8 lsll a, #imm8 2 2 2 3 3 3 *2 *2 *2 *4 *4 *4 0 0 0 0 0 0 long (a) ? arithmetic right barrel shift (a, r0) long (a) ? logical right barrel shift (a, r0) long (a) ? logical left barrel shift (a, r0) long (a) ? arithmetic right barrel shift (a, imm8) long (a) ? logical right barrel shift (a, imm8) long (a) ? logical left barrel shift (a, imm8) C C C C C C C C C C C C C C C C C C C C C C C C * * C * * C * * * * * * * * * * * * C C C C C C * * * * * * C C C C C C
mb90210 series 90 table 20 branch 1 [31 instructions] note: for (a), (c) and (d), refer to table 4 number of execution cycles in addressing modes and table 5 correction values for number of cycles for calculating actual number of cycles. *1: set to 3 when branch is executed, and 2 when branch is not executed. *2: 3 (c) + (b) *3: reads (word) of the branch destination address. *4: w pushes to stack (word), and r reads (word) of the branch destination address. *5: pushes to stack (word). *6: w pushes to stack (long), and r reads (long) of the branch destination address. *7: pushes to stack (long). mnemonic # ~ b operation lh ah istnzvcrmw bz/beq rel bnz/bne rel bc/blo rel bnc/bhs rel bn rel bp rel bv rel bnv rel bt rel bnt rel blt rel bge rel ble rel bgt rel bls rel bhi rel bra rel jmp @ a jmp addr16 jmp @ear jmp @eam jmpp @ear * 3 jmpp @eam * 3 jmpp addr24 call @ear * 4 call @eam * 4 call addr16 * 5 callv #vct4 * 5 callp @ear * 6 callp @eam * 6 callp addr24 * 7 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 1 3 2 2 + 2 2 + 4 2 2 + 3 1 2 2 + 4 *1 *1 *1 *1 *1 *1 *1 *1 *1 *1 *1 *1 *1 *1 *1 *1 *1 2 2 3 4 + (a) 3 4 + (a) 3 4 5 + (a) 5 5 7 8 + (a) 7 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (c) 0 (d) 0 (c) 2 (c) (c) 2 (c) 2 (c) *2 2 (c) branch if (z) = 1 branch if (z) = 0 branch if (c) = 1 branch if (c) = 0 branch if (n) = 1 branch if (n) = 0 branch if (v) = 1 branch if (v) = 0 branch if (t) = 1 branch if (t) = 0 branch if (v) xor (n) = 1 branch if (v) xor (n) = 0 branch if ((v) xor (n)) or (z) = 1 branch if ((v) xor (n)) or (z) = 0 branch if (c) or (z) = 1 branch if (c) or (z) = 0 branch unconditionally word (pc) ? (a) word (pc) ? addr16 word (pc) ? (ear) word (pc) ? (eam) word (pc) ? (ear), (pcb) ? (ear + 2) word (pc) ? (eam), (pcb) ? (eam + 2) word (pc) ? ad24 0 C 15, (pcb) ? ad24 16 C 23 word (pc) ? (ear) word (pc) ? (eam) word (pc) ? addr16 vector call instruction word (pc) ? (ear) 0 C 15 (pcb) ? (ear) 16 C 23 word (pc) ? (eam) 0 C 15 (pcb) ? (eam) 16 C 23 word (pc) ? addr0 C 15, (pcb) ? addr16 C 23 C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C
91 mb90210 series table 21 branch 2 [20 instructions] note: for (a) to (d), refer to table 4 number of execution cycles in addressing modes and table 5 correction values for number of cycles for calculating actual number of cycles. *1: set to 4 when branch is executed, and 3 when branch is not executed. *2: set to 5 when branch is executed, and 4 when branch is not executed. *3: set to 5 + (a) when branch is executed, and 4 + (a) when branch is not executed. *4: set to 6 + (a) when branch is executed, and 5 + (a) when branch is not executed. *5: set to 3 (b) + 2 (c) when an interrupt request is issued, and 6 (c) for return. *6: this is a high-speed interrupt return instruction. in the instruction, an interrupt request is detected. when an interrupt occurs, stack operation is not performed, with this instruction branching to the interrupt vector. *7: return from stack (word). *8: return from stack (long). mnemonic # ~ b operation lh ah istnzvcrmw cbne a, #imm8, rel cwbne a, #imm16, rel cbne ear, #imm8, rel cbne eam, #imm8, rel cwbne ear, #imm16, rel cwbne eam, #imm16, rel dbnz ear, rel dbnz eam, rel dwbnz ear, rel dwbnz eam, rel int #vct8 int addr16 intp addr24 int9 reti retiq * 6 link #imm8 unlink ret * 7 retp * 8 3 4 4 4 + 5 5 + 3 3 + 3 3 + 2 3 4 1 1 2 2 1 1 1 *1 *1 *1 *3 *1 *3 *2 *4 *2 *4 14 12 13 14 9 11 6 5 4 5 0 0 0 (b) 0 (c) 0 2 (b) 0 2 (c) 8 (c) 6 (c) 6 (c) 8 (c) 6 (c) *5 (c) (c) (c) (d) branch if byte (a) 1 imm8 branch if word (a) 1 imm16 branch if byte (ear) 1 imm8 branch if byte (eam) 1 imm8 branch if word (ear) 1 imm16 branch if word (eam) 1 imm16 byte (ear) = (ear) C 1, branch if (ear) 1 0 byte (eam) = (eam) C 1, branch if (eam) 1 0 word (ear) = (ear) C 1, branch if (ear) 1 0 word (eam) = (eam) C 1, branch if (eam) 1 0 software interrupt software interrupt software interrupt software interrupt return from interrupt return from interrupt stores old frame pointer in the beginning of the function, set new frame pointer, and reserves local pointer area restore old frame pointer from stack in the end of the function return from subroutine return from subroutine C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C r r r r * * C C C C C C C C C C C C C C s s s s * * C C C C C C C C C C C C C C C C C C * * C C C C * * * * * * * * * * C C C C * * C C C C * * * * * * * * * * C C C C * * C C C C * * * * * * * * * * C C C C * * C C C C * * * * * * C C C C C C C C * * C C C C C C C C C C C * C * C C C C C C C C C C
mb90210 series 92 table 22 miscellaneous control types (byte, word, long) [36 instructions] note: for (a) and (c), refer to table 4 number of execution cycles in addressing modes and table 5 correction values for number of cycles for calculating actual number of cycles. *1: pcb, adb, ssb, usb, and spb : 1 state dtb : 2 states dpr : 3 states *2: 3 + 4 (number of pops) *3: 3 + 4 (number of pushes) *4: (number of pops) (c), or (number of pushes) (c) *5: set to 3 when al is 0, 5 when al is not 0. *6: set to 4 when al is 0, 6 when al is not 0. *7: set to 5 when al is 0, 7 when al is not 0. mnemonic # ~ b operation lh ah istnzvcrmw pushw a pushw ah pushw ps pushw rlst popw a popw ah popw ps popw rlst jctx @a and ccr, #imm8 or ccr, #imm8 mov rp , #imm8 mov ilm, #imm8 movea rwi, ear movea rwi, eam movea a, ear movea a, eam addsp #imm8 addsp #imm16 mov a, brgl mov brg2, a mov brg2, #imm8 nop adb dtb pcb spb ncc cmr movw spcu, #imm16 movw spcl, #imm16 setspc clrspc btscn a btscns a btscnd a 1 1 1 2 1 1 1 2 1 2 2 2 2 2 2 + 2 2 + 2 3 2 2 3 1 1 1 1 1 1 1 4 4 2 2 2 2 2 3 3 3 *3 3 3 3 *2 9 3 3 2 2 3 2 + (a) 2 1 + (a) 3 3 *1 1 2 1 1 1 1 1 1 1 2 2 2 2 *5 *6 *7 (c) (c) (c) *4 (c) (c) (c) *4 6 (c) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 word (sp) ? (sp) C 2, ((sp)) ? (a) word (sp) ? (sp) C 2, ((sp)) ? (ah) word (sp) ? (sp) C 2, ((sp)) ? (ps) (ps) ? (ps) C 2n, ((sp)) ? (rlst) word (a) ? ((sp)), (sp) ? ( sp) + 2 word (ah) ? ((sp)), (sp) ? ( sp) + 2 word (ps) ? ((sp)), (sp) ? ( sp) + 2 (rlst) ? ((sp)), (sp) ? (sp) + 2n context switch instruction byte (ccr) ? (ccr) and imm8 byte (ccr) ? (ccr) or imm8 byte (rp) ? imm8 byte (ilm) ? imm8 word (rwi) ? ear word (rwi) ? eam word(a) ? ear word (a) ? eam word (sp) ? (sp) + ext (imm8) word (sp) ? (sp) + imm16 byte (a) ? (brgl) byte (brg2) ? (a) byte (brg2) ? imm8 no operation prefix code for accessing ad space prefix code for accessing dt space prefix code for accessing pc space prefix code for accessing sp space prefix code for no change in flag prefix for common register bank word (spcu) ? (imm16) word (spcl) ? (imm16) enables stack check operation. disables stack check operation. bit position of 1 in byte (a) from word (a) bit position ( 2) of 1 in byte (a) from word (a) bit position ( 4) of 1 in byte (a) from word (a) C C C C C C C C C C C C C C C C C C C z C C C C C C C C C C C C C z z z C C C C * C C C C C C C C C C * * C C * C C C C C C C C C C C C C C C C C C C C C C * C * * * C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C * C * * * C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C * C * * * C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C * C * * * C C C C C C C C * * * C C C C C C C C C C C C C C C C C C C C * C * * * C C C C C C C C * * * C C C C C C C C C C C * * * C C C C C C * C * * * C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C * C * * * C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C
93 mb90210 series table 23 bit manipulation instruction [21 instructions] note: for (b), refer to table 5 correction values for number of cycles for calculating actual number of cycles. *1: set to 5 when branch is executed, and 4 when branch is not executed. *2: 7 if conditions are met, 6 when conditions are not met. *3: indeterminate times *4: until conditions are met mnemonic # ~ b operation lh ah istnzvcrmw movb a, dir:bp movb a, addr16:bp movb a, io:bp movb dir:bp, a movb addr16:bp, a movb io:bp, a setb dir:bp setb addr16:bp setb io:bp clrb dir:bp clrb addr16:bp clrb io:bp bbc dir:bp, rel bbc addr16:bp, rel bbc io:bp, rel bbs dir:bp, rel bbs addr16:bp, rel bbs io:bp, rel sbbs addr16:bp, rel wbts io:bp wbtc io:bp 3 4 3 3 4 3 3 4 3 3 4 3 4 5 4 4 5 4 5 3 3 3 3 3 4 4 4 4 4 4 4 4 4 *1 *1 *1 *1 *1 *1 *2 *3 *3 (b) (b) (b) 2 (b) 2 (b) 2 (b) 2 (b) 2 (b) 2 (b) 2 (b) 2 (b) 2 (b) (b) (b) (b) (b) (b) (b) 2 (b) *4 *4 byte (a) ? (dir:bp) b byte (a) ? (addr16:bp) b byte (a) ? (io:bp) b bit (dir:bp) b ? (a) bit (addr16:bp) b ? (a) bit (io:bp) b ? (a) bit (dir:bp) b ? 1 bit (addr16:bp) b ? 1 bit (io:bp) b ? 1 bit (dir:bp) b ? 0 bit (addr16:bp) b ? 0 bit (io:bp) b ? 0 branch if (dir:bp) b = 0 branch if (addr16:bp) b = 0 branch if (io:bp) b = 0 branch if (dir:bp) b = 1 branch if (addr16:bp) b = 1 branch if (io:bp) b = 1 branch if (addr16:bp) b = 1, bit = 1 wait until (io:bp) b = 1 wait until (io:bp) b = 0 z z z C C C C C C C C C C C C C C C C C C * * * C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C * * * * * * C C C C C C C C C C C C C C C * * * * * * C C C C C C * * * * * * * C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C * * * * * * * * * C C C C C C * C C
mb90210 series 94 table 24 accumulator manipulation instruction (byte, word) [6 instructions] table 25 string instruction [10 instructions] m: rw0 value (counter value) *1: 3 when rw0 is 0, 2 + 6 (rw0) when count out, and 6n + 4 when matched *2: 4 when rw0 is 0, otherwise 2 + 6 (rw0) *3: (b) (rw0) *4: (b) n *5: (b) (rw0) *6: (c) (rw0) *7: (c) n *8: (c) (rw0) mnemonic # ~ b operation lh ah istnzvcrmw swap swapw/xchw al, ah ext extw zext zextw 1 1 1 1 1 1 3 2 1 2 1 1 0 0 0 0 0 0 byte (a) 0 C 7 ? (a) 8 C 15 word (ah) ? (al) byte sign-extension word sign-extension byte zero-extension word zero-extension C C x C z C C * C x C z C C C C C C C C C C C C C C C C C C C C * * r r C C * * * * C C C C C C C C C C C C C C C C C C mnemonic # ~ b operation lh ah istnzvcrmw movs/movsi movsd sceq/sceqi sceqd fisl/filsi 2 2 2 2 2 *2 *2 *1 *1 5m + 6 *3 *3 *4 *4 *5 byte transfer @ah + ? @al +, counter = rw0 byte transfer @ah C ? @al C, counter = rw0 byte search (@ah +) C al, counter = rw0 byte search (@ah C) C al, counter = rw0 byte fill @ah + ? al, counter = rw0 C C C C C C C C C C C C C C C C C C C C C C C C C C C * * * C C * * * C C * * C C C * * C C C C C C movsw/movswi movswd scweq/scweqi scweqd filsw/filswi 2 2 2 2 2 *2 *2 *1 *1 5m + 6 *6 *6 *7 *7 *8 word transfer @ah + ? @al +, counter = rw0 word transfer @ah C ? @al C, counter = rw0 word search (@ah +) C al, counter = rw0 word search (@ah C) C al, counter = rw0 word fill @ah + ? al, counter = rw0 C C C C C C C C C C C C C C C C C C C C C C C C C C C * * * C C * * * C C * * C C C * * C C C C C C
95 mb90210 series table 26 multiple data transfer instructions [18 instruction] *1: 256 when 5 + imm8 5, imm8 is 0. *2: 256 when 5 + imm8 5 + (a), imm8 is 0. *3: (number of transfer cycles) (b) 2 *4: (number of transfer cycles) (c) 2 *5: the bank register specified by bnk is the same as that for the movs instruction. mnemonic # ~ b operation lh ah istnzvcrmw movm @a, @rli, #imm8 3 *1 *3 multiple data transfer byte ((a)) ? ((rli)) CCCCCCCCC C movm @a, eam, #imm8 3 + *2 *3 multiple data transfer byte ((a)) ? (eam) CCCCCCCCC C movm addr16, @rli, #imm8 5 *1 *3 multiple data transfer byte (addr16) ? ((rli)) CCCCCCCCC C movm addr16, @eam, #imm8 5 + *2 *3 multiple data transfer byte (addr16) ? (eam) CCCCCCCCC C movmw @a, @rli, #imm8 3 *1 *4 multiple data transfer word ((a)) ? ((rli)) CCCCCCCCC C movmw @a, eam, #imm8 3 + *2 *4 multiple data transfer word ((a)) ? (eam) CCCCCCCCC C movmwaddr16, @rli, #imm8 5 *1 *4 multiple data transfer word (addr16) ? ((rli)) CCCCCCCCC C movmwaddr16, @eam, #imm8 5 + *2 *4 multiple data transfer word (addr16) ? (eam) CCCCCCCCC C movm @rli, @a, #imm8 3 *1 *3 multiple data transfer byte ((rli)) ? ((a)) CCCCCCCCC C movm @eam, a, #imm8 3 + *2 *3 multiple data transfer byte (eam) ? ((a)) CCCCCCCCC C movm @rli, addr16, #imm8 5 *1 *3 multiple data transfer byte ((rli)) ? (addr16) CCCCCCCCC C movm @eam, addr16, #imm8 5 + *2 *3 multiple data transfer byte (eam) ? (addr16) CCCCCCCCC C movmw @rli, @a, #imm8 3 *1 *4 multiple data transfer word ((rli)) ? ((a)) CCCCCCCCC C movmw @eam, a, #imm8 3 + *2 *4 multiple data transfer word (eam) ? ((a)) CCCCCCCCC C movmw@rli, addr16, #imm8 5 *1 *4 multiple data transfer word ((rli)) ? (addr16) CCCCCCCCC C movmw@eam, addr16, #imm8 5 + *2 *4 multiple data transfer word (eam) ? (addr16) CCCCCCCCC C movm bnk: addr16, bnk: addr16, #imm8 * 5 7 *1 *3 multiple data transfer byte (bnk: addr16) ? (bnk: addr16) CCCCCCCCC C movmw bnk: addr16, bnk: addr16, #imm8 * 5 7 *1 *4 multiple data transfer word (bnk: addr16) ? (bnk: addr16) CCCCCCCCC C
mb90210 series 96 n ordering information part number type package remarks mb90214 MB90P214A mb90p214b mb90214pf mb90p214pf mb90p214bpf 80-pin plastic qfp (fpt-80p-m06) mb90w214a mb90w214b mb90w214zf mb90w214bzf 80-pin ceramic qfp (fpt-80c-c02) only es level mb90v210 mb90v210cr 256-pin ceramic pga (pga-256c-a02) for evaluation
97 mb90210 series n package dimensions "a" lead no. (.031.008) 0.800.20 0.30(.012) 0.25(.010) 80 65 64 41 40 25 24 1 22.300.40(.878.016) 18.40(.724)ref m 0.16(.006) (.014.004) 0.350.10 0.80(.0315)typ (.705.016) (.551.008) 14.000.20 17.900.40 20.000.20(.787.008) 23.900.40(.941.016) index 0.150.05(.006.002) (stand off) 0.05(.002)min 3.35(.132)max (.642.016) 16.300.40 ref 12.00(.472) details of "b" part 0 10 details of "a" part 0.18(.007)max 0.58(.023)max 0.10(.004) "b" 1994 fujitsu limited f80010s-3c-2 c (mounting height) C0.20 +0.50 +.020 C.008 C.006 +.018 +0.45 C0.15 (.0315.008) (.878.010) (stand off) (.057.008) 0.350.10 (.941.012) 20.00 .787 .551 14.00 ?8.89(.350)typ 0.800.20 22.300.25 1.450.20 (.014.004) 0.80(.0315)typ 18.40(.724) ref 23.900.30 (.006.002) 0.150.05 3.30(.130)max 0.05(.002)min ref 12.00(.472) (.642.010) 16.300.25 (.705.012) 17.900.30 index area 1994 fujitsu limited f80018sc-1-2 c (mounting height) 80-pin plastic qfp (fpt-80p-m06) dimensions in mm (inches) dimensions in mm (inches) 80-pin ceramic qfp (fpt-80c-c02)
mb90210 series 98 memo
99 mb90210 series memo
mb90210 series 10 fujitsu limited for further information please contact: japan fujitsu limited corporate global business support division electronic devices kawasaki plant, 4-1-1, kamikodanaka nakahara-ku, kawasaki-shi kanagawa 211-88, japan tel: (044) 754-3763 fax: (044) 754-3329 http://www.fujitsu.co.jp/ north and south america fujitsu microelectronics, inc. semiconductor division 3545 north first street san jose, ca 95134-1804, u.s.a. tel: (408) 922-9000 fax: (408) 922-9179 customer response center mon. - fri.: 7 am - 5 pm (pst) tel: (800) 866-8608 fax: (408) 922-9179 http://www.fujitsumicro.com/ europe fujitsu mikroelektronik gmbh am siebenstein 6-10 d-63303 dreieich-buchschlag germany tel: (06103) 690-0 fax: (06103) 690-122 http://www.fujitsu-ede.com/ asia pacific fujitsu microelectronics asia pte ltd #05-08, 151 lorong chuan new tech park singapore 556741 tel: (65) 281-0770 fax: (65) 281-0220 http://www.fmap.com.sg/ f9710 ? fujitsu limited printed in japan all rights reserved. the contents of this document are subject to change without notice. customers are advised to consult with fujitsu sales representatives before ordering. the information and circuit diagrams in this document presented as examples of semiconductor device applications, and are not intended to be incorporated in devices for actual use. also, fujitsu is unable to assume responsibility for infringement of any patent rights or other rights of third parties arising from the use of this information or circuit diagrams. fujitsu semiconductor devices are intended for use in standard applications (computers, office automation and other office equipment, industrial, communications, and measurement equipment, personal or household devices, etc.). caution: customers considering the use of our products in special applications where failure or abnormal operation may directly affect human lives or cause physical injury or property damage, or where extremely high levels of reliability are demanded (such as aerospace systems, atomic energy controls, sea floor repeaters, vehicle operating controls, medical devices for life support, etc.) are requested to consult with fujitsu sales representatives before such use. the company will not be responsible for damages arising from such use without prior approval. any semiconductor devices have inherently a certain rate of failure. you must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. if any products described in this document represent goods or technologies subject to certain restrictions on export under the foreign exchange and foreign trade control law of japan, the prior authorization by japanese government should be required for export of those products from japan.

▲Up To Search▲

Price & Availability of MB90P214A

	To Download MB90P214A Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .